[llvm] r199295 - Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
Craig Topper
craig.topper at gmail.com
Tue Jan 14 21:02:02 PST 2014
Author: ctopper
Date: Tue Jan 14 23:02:02 2014
New Revision: 199295
URL: http://llvm.org/viewvc/llvm-project?rev=199295&view=rev
Log:
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
Modified:
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
llvm/trunk/utils/TableGen/X86RecognizableInstr.h
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=199295&r1=199294&r2=199295&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Tue Jan 14 23:02:02 2014
@@ -232,6 +232,7 @@ RecognizableInstr::RecognizableInstr(Dis
Form = byteFromRec(Rec, "FormBits");
HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
+ HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
@@ -254,10 +255,6 @@ RecognizableInstr::RecognizableInstr(Dis
Operands = &insn.Operands.OperandList;
- IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD ||
- Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
- (Name.find("16") == Name.npos)) ||
- (Name.find("CRC32") != Name.npos);
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX
@@ -558,9 +555,9 @@ void RecognizableInstr::handleOperand(bo
Spec->operands[operandIndex].encoding = encodingFromString(typeName,
HasOpSizePrefix);
Spec->operands[operandIndex].type = typeFromString(typeName,
- IsSSE,
HasREX_WPrefix,
- HasOpSizePrefix);
+ HasOpSizePrefix,
+ HasOpSize16Prefix);
++operandIndex;
++physicalOperandIndex;
@@ -1164,36 +1161,34 @@ void RecognizableInstr::emitDecodePath(D
#define TYPE(str, type) if (s == str) return type;
OperandType RecognizableInstr::typeFromString(const std::string &s,
- bool isSSE,
bool hasREX_WPrefix,
- bool hasOpSizePrefix) {
- if (isSSE) {
- // For SSE instructions, we ignore the OpSize prefix and force operand
- // sizes.
- TYPE("GR16", TYPE_R16)
- TYPE("GR32", TYPE_R32)
- TYPE("GR64", TYPE_R64)
- }
+ bool hasOpSizePrefix,
+ bool hasOpSize16Prefix) {
if(hasREX_WPrefix) {
// For instructions with a REX_W prefix, a declared 32-bit register encoding
// is special.
TYPE("GR32", TYPE_R32)
}
- if(!hasOpSizePrefix) {
- // For instructions without an OpSize prefix, a declared 16-bit register or
+ if(hasOpSizePrefix) {
+ // For instructions with an OpSize prefix, a declared 16-bit register or
+ // immediate encoding is special.
+ TYPE("GR16", TYPE_Rv)
+ TYPE("i16imm", TYPE_IMMv)
+ }
+ if(hasOpSize16Prefix) {
+ // For instructions with an OpSize16 prefix, a declared 32-bit register or
// immediate encoding is special.
- TYPE("GR16", TYPE_R16)
- TYPE("i16imm", TYPE_IMM16)
+ TYPE("GR32", TYPE_Rv)
}
TYPE("i16mem", TYPE_Mv)
- TYPE("i16imm", TYPE_IMMv)
+ TYPE("i16imm", TYPE_IMM16)
TYPE("i16i8imm", TYPE_IMMv)
- TYPE("GR16", TYPE_Rv)
+ TYPE("GR16", TYPE_R16)
TYPE("i32mem", TYPE_Mv)
TYPE("i32imm", TYPE_IMMv)
TYPE("i32i8imm", TYPE_IMM32)
TYPE("u32u8imm", TYPE_IMM32)
- TYPE("GR32", TYPE_Rv)
+ TYPE("GR32", TYPE_R32)
TYPE("GR32orGR64", TYPE_R32)
TYPE("i64mem", TYPE_Mv)
TYPE("i64i32imm", TYPE_IMM64)
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.h?rev=199295&r1=199294&r2=199295&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.h (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.h Tue Jan 14 23:02:02 2014
@@ -46,6 +46,8 @@ private:
uint8_t Form;
/// The hasOpSizePrefix field from the record
bool HasOpSizePrefix;
+ /// The hasOpSize16Prefix field from the record
+ bool HasOpSize16Prefix;
/// The hasAdSizePrefix field from the record
bool HasAdSizePrefix;
/// The hasREX_WPrefix field from the record
@@ -89,9 +91,7 @@ private:
std::string Name;
/// The AT&T AsmString for the instruction
std::string AsmString;
-
- /// Indicates whether the instruction is SSE
- bool IsSSE;
+
/// Indicates whether the instruction should be emitted into the decode
/// tables; regardless, it will be emitted into the instruction info table
bool ShouldBeEmitted;
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