[llvm] r199248 - Revert "[AArch64] Added vselect patterns with float and double types"

[Rafael Espindola]

Author: rafael
Date: Tue Jan 14 13:24:08 2014
New Revision: 199248

URL: http://llvm.org/viewvc/llvm-project?rev=199248&view=rev
Log:
Revert "[AArch64] Added vselect patterns with float and double types"

This reverts commit r199242.

It is causing CodeGen/AArch64/neon-bsl.ll to fail.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
    llvm/trunk/test/CodeGen/AArch64/neon-bsl.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td?rev=199248&r1=199247&r2=199248&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td Tue Jan 14 13:24:08 2014
@@ -473,10 +473,6 @@ multiclass Neon_bitwise3V_patterns<SDPat
             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
-  def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
-            (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
-  def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
-            (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 
   // Allow to match BSL instruction pattern with non-constant operand
   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),

Modified: llvm/trunk/test/CodeGen/AArch64/neon-bsl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-bsl.ll?rev=199248&r1=199247&r2=199248&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-bsl.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-bsl.ll Tue Jan 14 13:24:08 2014
@@ -220,14 +220,3 @@ entry:
   ret <2 x double> %vbsl3.i
 }
 
-define <2 x double> @bsl2xf64(<2 x i1> %v1, <2 x double> %v2, <2 x double> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-  %1 = select <2 x i1> %v1, <2 x double> %v2, <2 x double> %v3
-  ret <2 x double> %1
-}
-
-define <4 x float> @bsl4xf32(<4 x i1> %v1, <4 x float> %v2, <4 x float> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-  %1 = select <4 x i1> %v1, <4 x float> %v2, <4 x float> %v3
-  ret <4 x float> %1
-}