[Patch] [ThumbV8] Fix assertion fails due to inconsistent CPSR liveness of IT blocks

[Weiming Zhao]

Hi Andrew,

 

Thanks for review.

Committed revision 199127

 

Weiming

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

From: Andrew Trick [mailto:atrick at apple.com] 
Sent: Friday, January 10, 2014 11:53 PM
To: weimingz at codeaurora.org
Cc: llvm commits
Subject: Re: [Patch] [ThumbV8] Fix assertion fails due to inconsistent CPSR
liveness of IT blocks

 

 

On Jan 3, 2014, at 12:08 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:





Hi,

 

Attached patch fixes assertion fails due to inconsistent CPSR liveness of IT
blocks.

See bug  <http://llvm.org/bugs/show_bug.cgi?id=18369>
http://llvm.org/bugs/show_bug.cgi?id=18369

 

The issue is caused when Post-RA scheduler reorders a bundle instruction (IT
block) and a vseleq. However, it only flips the CPSR liveness of the bundle
instruction, leaves the instructions inside the bundle unchanged, which
causes inconstancy.

 

This inconsistency causes Thumb2SizeReduction.cpp::ReduceMBB() crash because
CPSR is expected to be LIVE for VSELEQD.
 
There is a FIXME in Thumb2SizeReduction.cpp that tries to fixup such
inconsistency, but it seems incomplete. This patch augments the fixup.
Please help to review it.
 
Thanks,
Weiming

 

 

Hi Weiming,

 

Your fix seems safe to me.

 

-Andy

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