[llvm] r198914 - ARM IAS: support implicit immediate 0s for {LD, ST}R{B, }T
Jim Grosbach
grosbach at apple.com
Fri Jan 10 10:15:18 PST 2014
This is not the right way to do this. These are assembly aliases, not distinct instruction encodings. They should be implemented as such. There should never be two instruction definitions that map to the same encoding.
-Jim
On Jan 9, 2014, at 8:38 PM, Saleem Abdulrasool <compnerd at compnerd.org> wrote:
> Author: compnerd
> Date: Thu Jan 9 22:38:31 2014
> New Revision: 198914
>
> URL: http://llvm.org/viewvc/llvm-project?rev=198914&view=rev
> Log:
> ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
>
> The ARM ARM indicates the mnemonics as follows:
>
> ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
> ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
> strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
> strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
>
> This improves the parser to deal with the implicit immediate 0 for the mnemonics
> as per the specification.
>
> Thanks to Joerg Sonnenberger for the tests!
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/test/MC/ARM/arm_addrmode2.s
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=198914&r1=198913&r2=198914&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jan 9 22:38:31 2014
> @@ -2444,23 +2444,28 @@ def LDRT_POST_REG : AI2ldstidx<1, 0, 0,
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> -def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> - (ins addr_offset_none:$addr, am2offset_imm:$offset),
> - IndexModePost, LdFrm, IIC_iLoad_ru,
> - "ldrt", "\t$Rt, $addr, $offset",
> - "$addr.base = $Rn_wb", []> {
> +class LDRTImmediate<bit has_offset, string args, dag iops>
> + : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,
> + IndexModePost, LdFrm, IIC_iLoad_ru,
> + "ldrt", args, "$addr.base = $Rn_wb", []> {
> // {12} isAdd
> // {11-0} imm12/Rm
> bits<14> offset;
> bits<4> addr;
> let Inst{25} = 0;
> - let Inst{23} = offset{12};
> + let Inst{23} = !if(has_offset, offset{12}, 1);
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr;
> - let Inst{11-0} = offset{11-0};
> + let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> +def LDRT_POST_IMM
> + : LDRTImmediate<1, "\t$Rt, $addr, $offset",
> + (ins addr_offset_none:$addr, am2offset_imm:$offset)>;
> +def LDRT_POST_IMM_0
> + : LDRTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;
> +
> def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> (ins addr_offset_none:$addr, am2offset_reg:$offset),
> IndexModePost, LdFrm, IIC_iLoad_bh_ru,
> @@ -2480,23 +2485,28 @@ def LDRBT_POST_REG : AI2ldstidx<1, 1, 0,
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> -def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> - (ins addr_offset_none:$addr, am2offset_imm:$offset),
> +class LDRBTImmediate<bit has_offset, string args, dag iops>
> + : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,
> IndexModePost, LdFrm, IIC_iLoad_bh_ru,
> - "ldrbt", "\t$Rt, $addr, $offset",
> - "$addr.base = $Rn_wb", []> {
> + "ldrbt", args, "$addr.base = $Rn_wb", []> {
> // {12} isAdd
> // {11-0} imm12/Rm
> bits<14> offset;
> bits<4> addr;
> let Inst{25} = 0;
> - let Inst{23} = offset{12};
> + let Inst{23} = !if(has_offset, offset{12}, 1);
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr;
> - let Inst{11-0} = offset{11-0};
> + let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> +def LDRBT_POST_IMM
> + : LDRBTImmediate<1, "\t$Rt, $addr, $offset",
> + (ins addr_offset_none:$addr, am2offset_imm:$offset)>;
> +def LDRBT_POST_IMM_0
> + : LDRBTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;
> +
> multiclass AI3ldrT<bits<4> op, string opc> {
> def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
> (ins addr_offset_none:$addr, postidx_imm8:$offset),
> @@ -2748,23 +2758,27 @@ def STRBT_POST_REG : AI2ldstidx<0, 1, 0,
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> -def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
> - (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
> - IndexModePost, StFrm, IIC_iStore_bh_ru,
> - "strbt", "\t$Rt, $addr, $offset",
> - "$addr.base = $Rn_wb", []> {
> +class STRBTImmediate<bit has_offset, string args, dag iops>
> + : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,
> + IIC_iStore_bh_ru, "strbt", args, "$addr.base = $Rn_wb", []> {
> // {12} isAdd
> // {11-0} imm12/Rm
> bits<14> offset;
> bits<4> addr;
> let Inst{25} = 0;
> - let Inst{23} = offset{12};
> + let Inst{23} = !if(has_offset, offset{12}, 1);
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr;
> - let Inst{11-0} = offset{11-0};
> + let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> +def STRBT_POST_IMM
> + : STRBTImmediate<1, "\t$Rt, $addr, $offset",
> + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)>;
> +def STRBT_POST_IMM_0
> + : STRBTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr)>;
> +
> let mayStore = 1, neverHasSideEffects = 1 in {
> def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
> (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
> @@ -2785,22 +2799,26 @@ def STRT_POST_REG : AI2ldstidx<0, 0, 0,
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> -def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
> - (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
> - IndexModePost, StFrm, IIC_iStore_ru,
> - "strt", "\t$Rt, $addr, $offset",
> - "$addr.base = $Rn_wb", []> {
> +class STRTImmediate<bit has_offset, string args, dag iops>
> + : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,
> + IIC_iStore_ru, "strt", args, "$addr.base = $Rn_wb", []> {
> // {12} isAdd
> // {11-0} imm12/Rm
> bits<14> offset;
> bits<4> addr;
> let Inst{25} = 0;
> - let Inst{23} = offset{12};
> + let Inst{23} = !if(has_offset, offset{12}, 1);
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr;
> - let Inst{11-0} = offset{11-0};
> + let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
> let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
> +
> +def STRT_POST_IMM
> + : STRTImmediate<1, "\t$Rt, $addr, $offset",
> + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)>;
> +def STRT_POST_IMM_0
> + : STRTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr)>;
> }
>
>
>
> Modified: llvm/trunk/test/MC/ARM/arm_addrmode2.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?rev=198914&r1=198913&r2=198914&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/arm_addrmode2.s (original)
> +++ llvm/trunk/test/MC/ARM/arm_addrmode2.s Thu Jan 9 22:38:31 2014
> @@ -4,27 +4,35 @@
> @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
> @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
> @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
> +@ CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4]
> @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
> @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
> @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
> +@ CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4]
> @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
> @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
> @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
> +@ CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4]
> @ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
> @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
> @ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
> +@ CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4]
> ldrt r1, [r0], r2
> ldrt r1, [r0], r2, lsr #3
> ldrt r1, [r0], #4
> + ldrt r1, [r0]
> ldrbt r1, [r0], r2
> ldrbt r1, [r0], r2, lsr #3
> ldrbt r1, [r0], #4
> + ldrbt r1, [r0]
> strt r1, [r0], r2
> strt r1, [r0], r2, lsr #3
> strt r1, [r0], #4
> + strt r1, [r0]
> strbt r1, [r0], r2
> strbt r1, [r0], r2, lsr #3
> strbt r1, [r0], #4
> + strbt r1, [r0]
>
> @ Pre-indexed
> @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
>
>
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