[llvm] r198914 - ARM IAS: support implicit immediate 0s for {LD, ST}R{B, }T
Oliver Stannard
oliver.stannard at arm.com
Fri Jan 10 06:26:37 PST 2014
Hi Saleem,
It seems this commit introduced a regression.
Before this commit, I get:
$ echo "0x00,0x10,0xa0,0x04" | llvm-mc -mcpu=cortex-a15 -triple armv7
-disassemble
.text
strteq r1, [r0], #0
After this commit, I get:
$ echo "0x00,0x10,0xa0,0x04" | llvm-mc -mcpu=cortex-a15 -triple armv7
-disassemble
.text
strtUnknown condition code
UNREACHABLE executed at
/work/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h:86!
0 llvm-mc 0x00000000006567f2
1 llvm-mc 0x0000000000656429
2 libpthread.so.0 0x00007f18c076a8f0
3 libc.so.6 0x00007f18bfa56b25 gsignal + 53
4 libc.so.6 0x00007f18bfa5a670 abort + 384
5 llvm-mc 0x0000000000639cbc
6 llvm-mc 0x0000000000573a61
7 llvm-mc 0x000000000057774c
8 llvm-mc 0x000000000057d20e
9 llvm-mc 0x0000000000580906
10 llvm-mc 0x00000000005d776b
11 llvm-mc 0x000000000041998c
12 llvm-mc 0x000000000040fbf5
13 libc.so.6 0x00007f18bfa41c4d __libc_start_main + 253
14 llvm-mc 0x000000000041369d
Stack dump:
0. Program arguments: /work/llvm/bin/llvm-mc -mcpu=cortex-a15 -triple
armv7 -disassemble
Aborted
Would it be possible to fix this regression (and add the necessary test
cases that trigger this bug)?
Thank,
Oliver
-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Saleem Abdulrasool
Sent: 10 January 2014 04:39
To: llvm-commits at cs.uiuc.edu
Subject: [llvm] r198914 - ARM IAS: support implicit immediate 0s for {LD,
ST}R{B, }T
Author: compnerd
Date: Thu Jan 9 22:38:31 2014
New Revision: 198914
URL: http://llvm.org/viewvc/llvm-project?rev=198914&view=rev
Log:
ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:
ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
This improves the parser to deal with the implicit immediate 0 for the
mnemonics
as per the specification.
Thanks to Joerg Sonnenberger for the tests!
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/test/MC/ARM/arm_addrmode2.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.t
d?rev=198914&r1=198913&r2=198914&view=diff
============================================================================
==
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jan 9 22:38:31 2014
@@ -2444,23 +2444,28 @@ def LDRT_POST_REG : AI2ldstidx<1, 0, 0,
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
- (ins addr_offset_none:$addr, am2offset_imm:$offset),
- IndexModePost, LdFrm, IIC_iLoad_ru,
- "ldrt", "\t$Rt, $addr, $offset",
- "$addr.base = $Rn_wb", []> {
+class LDRTImmediate<bit has_offset, string args, dag iops>
+ : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,
+ IndexModePost, LdFrm, IIC_iLoad_ru,
+ "ldrt", args, "$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
- let Inst{23} = offset{12};
+ let Inst{23} = !if(has_offset, offset{12}, 1);
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
- let Inst{11-0} = offset{11-0};
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
+def LDRT_POST_IMM
+ : LDRTImmediate<1, "\t$Rt, $addr, $offset",
+ (ins addr_offset_none:$addr, am2offset_imm:$offset)>;
+def LDRT_POST_IMM_0
+ : LDRTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;
+
def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, LdFrm, IIC_iLoad_bh_ru,
@@ -2480,23 +2485,28 @@ def LDRBT_POST_REG : AI2ldstidx<1, 1, 0,
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
- (ins addr_offset_none:$addr, am2offset_imm:$offset),
+class LDRBTImmediate<bit has_offset, string args, dag iops>
+ : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,
IndexModePost, LdFrm, IIC_iLoad_bh_ru,
- "ldrbt", "\t$Rt, $addr, $offset",
- "$addr.base = $Rn_wb", []> {
+ "ldrbt", args, "$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
- let Inst{23} = offset{12};
+ let Inst{23} = !if(has_offset, offset{12}, 1);
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
- let Inst{11-0} = offset{11-0};
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
+def LDRBT_POST_IMM
+ : LDRBTImmediate<1, "\t$Rt, $addr, $offset",
+ (ins addr_offset_none:$addr, am2offset_imm:$offset)>;
+def LDRBT_POST_IMM_0
+ : LDRBTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;
+
multiclass AI3ldrT<bits<4> op, string opc> {
def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
(ins addr_offset_none:$addr, postidx_imm8:$offset),
@@ -2748,23 +2758,27 @@ def STRBT_POST_REG : AI2ldstidx<0, 1, 0,
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
- (ins GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset),
- IndexModePost, StFrm, IIC_iStore_bh_ru,
- "strbt", "\t$Rt, $addr, $offset",
- "$addr.base = $Rn_wb", []> {
+class STRBTImmediate<bit has_offset, string args, dag iops>
+ : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,
+ IIC_iStore_bh_ru, "strbt", args, "$addr.base = $Rn_wb", []>
{
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
- let Inst{23} = offset{12};
+ let Inst{23} = !if(has_offset, offset{12}, 1);
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
- let Inst{11-0} = offset{11-0};
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
+def STRBT_POST_IMM
+ : STRBTImmediate<1, "\t$Rt, $addr, $offset",
+ (ins GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset)>;
+def STRBT_POST_IMM_0
+ : STRBTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt,
addr_offset_none:$addr)>;
+
let mayStore = 1, neverHasSideEffects = 1 in {
def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr,
am2offset_reg:$offset),
@@ -2785,22 +2799,26 @@ def STRT_POST_REG : AI2ldstidx<0, 0, 0,
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
- (ins GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset),
- IndexModePost, StFrm, IIC_iStore_ru,
- "strt", "\t$Rt, $addr, $offset",
- "$addr.base = $Rn_wb", []> {
+class STRTImmediate<bit has_offset, string args, dag iops>
+ : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,
+ IIC_iStore_ru, "strt", args, "$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
- let Inst{23} = offset{12};
+ let Inst{23} = !if(has_offset, offset{12}, 1);
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
- let Inst{11-0} = offset{11-0};
+ let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
+
+def STRT_POST_IMM
+ : STRTImmediate<1, "\t$Rt, $addr, $offset",
+ (ins GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset)>;
+def STRT_POST_IMM_0
+ : STRTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt,
addr_offset_none:$addr)>;
}
Modified: llvm/trunk/test/MC/ARM/arm_addrmode2.s
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?r
ev=198914&r1=198913&r2=198914&view=diff
============================================================================
==
--- llvm/trunk/test/MC/ARM/arm_addrmode2.s (original)
+++ llvm/trunk/test/MC/ARM/arm_addrmode2.s Thu Jan 9 22:38:31 2014
@@ -4,27 +4,35 @@
@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
+@ CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4]
@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
+@ CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4]
@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
+@ CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4]
@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
+@ CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4]
ldrt r1, [r0], r2
ldrt r1, [r0], r2, lsr #3
ldrt r1, [r0], #4
+ ldrt r1, [r0]
ldrbt r1, [r0], r2
ldrbt r1, [r0], r2, lsr #3
ldrbt r1, [r0], #4
+ ldrbt r1, [r0]
strt r1, [r0], r2
strt r1, [r0], r2, lsr #3
strt r1, [r0], #4
+ strt r1, [r0]
strbt r1, [r0], r2
strbt r1, [r0], r2, lsr #3
strbt r1, [r0], #4
+ strbt r1, [r0]
@ Pre-indexed
@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
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