[llvm] r198862 - [SystemZ] Fix RNSBG bug introduced by r197802

[Richard Sandiford]

Author: rsandifo
Date: Thu Jan  9 05:28:53 2014
New Revision: 198862

URL: http://llvm.org/viewvc/llvm-project?rev=198862&view=rev
Log:
[SystemZ] Fix RNSBG bug introduced by r197802

The zext handling added in r197802 wasn't right for RNSBG.  This patch
restricts it to ROSBG, RXSBG and RISBG.  (The tests for RISBG were added
in r197802 since RISBG was the motivating example.)

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/SystemZ/rnsbg-01.ll
    llvm/trunk/test/CodeGen/SystemZ/rosbg-01.ll
    llvm/trunk/test/CodeGen/SystemZ/rxsbg-01.ll

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=198862&r1=198861&r2=198862&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Jan  9 05:28:53 2014
@@ -769,15 +769,17 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
     RxSBG.Input = N.getOperand(0);
     return true;
 
-  case ISD::ZERO_EXTEND: {
-    // Restrict the mask to the extended operand.
-    unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
-    if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
-      return false;
+  case ISD::ZERO_EXTEND:
+    if (RxSBG.Opcode != SystemZ::RNSBG) {
+      // Restrict the mask to the extended operand.
+      unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
+      if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
+        return false;
 
-    RxSBG.Input = N.getOperand(0);
-    return true;
-  }
+      RxSBG.Input = N.getOperand(0);
+      return true;
+    }
+    // Fall through.
     
   case ISD::SIGN_EXTEND: {
     // Check that the extension bits are don't-care (i.e. are masked out

Modified: llvm/trunk/test/CodeGen/SystemZ/rnsbg-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/rnsbg-01.ll?rev=198862&r1=198861&r2=198862&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/rnsbg-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/rnsbg-01.ll Thu Jan  9 05:28:53 2014
@@ -255,3 +255,14 @@ define i64 @f22(i64 %a, i64 %b) {
   %and = and i64 %a, %rotlorb
   ret i64 %and
 }
+
+; Check the handling of zext and AND, which isn't suitable for RNSBG.
+define i64 @f23(i64 %a, i32 %b) {
+; CHECK-LABEL: f23:
+; CHECK-NOT: rnsbg
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  %ext = zext i32 %add to i64
+  %and = and i64 %a, %ext
+  ret i64 %and
+}

Modified: llvm/trunk/test/CodeGen/SystemZ/rosbg-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/rosbg-01.ll?rev=198862&r1=198861&r2=198862&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/rosbg-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/rosbg-01.ll Thu Jan  9 05:28:53 2014
@@ -108,3 +108,14 @@ define i64 @f11(i64 %a, i64 %b) {
   %or = or i64 %a, %andb
   ret i64 %or
 }
+
+; Check the handling of zext and OR, which can use ROSBG.
+define i64 @f12(i64 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: rosbg %r2, %r3, 32, 63, 0
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  %ext = zext i32 %add to i64
+  %or = or i64 %a, %ext
+  ret i64 %or
+}

Modified: llvm/trunk/test/CodeGen/SystemZ/rxsbg-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/rxsbg-01.ll?rev=198862&r1=198861&r2=198862&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/rxsbg-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/rxsbg-01.ll Thu Jan  9 05:28:53 2014
@@ -110,3 +110,14 @@ define i64 @f11(i64 %a, i64 %b) {
   %xor = xor i64 %a, %andb
   ret i64 %xor
 }
+
+; Check the handling of zext and XOR, which can use ROSBG.
+define i64 @f12(i64 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: rxsbg %r2, %r3, 32, 63, 0
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  %ext = zext i32 %add to i64
+  %xor = xor i64 %a, %ext
+  ret i64 %xor
+}