[llvm] r198778 - [x86] Remove OpSize16 flag from MOV32r0
David Woodhouse
dwmw2 at infradead.org
Wed Jan 8 10:38:27 PST 2014
Author: dwmw2
Date: Wed Jan 8 12:38:26 2014
New Revision: 198778
URL: http://llvm.org/viewvc/llvm-project?rev=198778&view=rev
Log:
[x86] Remove OpSize16 flag from MOV32r0
It's not a real instruction any more and doesn't need encoding information.
Modified:
llvm/trunk/lib/Target/X86/X86InstrCompiler.td
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=198778&r1=198777&r2=198778&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Jan 8 12:38:26 2014
@@ -223,8 +223,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pse
let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
isPseudo = 1 in
def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
- [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, OpSize16,
- Sched<[WriteZero]>;
+ [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
// Other widths can also make use of the 32-bit xor, which may have a smaller
// encoding and avoid partial register updates.
More information about the llvm-commits
mailing list