[PATCH] [AArch64] Add register spill code for large super registers such as DPair, DTriple ...

[Hao Liu]

Hi Jakob,

Thanks for informing me about that.

I tried inline assembly to force spilling. But such spill is currently
implemented by stp and str, not vector store such as st1. I think this kind
of spill is different from the spill in StoreRegToStackSlot() ( in
AArch64InstrInfo.cpp ).

May example:
$ cat spill.ll
define void @f(double* nocapture %p) nounwind ssp {
entry:
  tail call void asm sideeffect "", "~{q8}"() nounwind
  ret void
}

$ llc -march=aarch64 -mattr=+neon < spill.ll
f:                                     // @f
// BB#0:                                // %entry
	sub	sp, sp, #32
	stp	d9, d10, [sp, #16]      // 16-byte Folded Spill
	str	d8, [sp, #8]            // 8-byte Folded Spill
	//APP
	//NO_APP
	ldr	d8, [sp, #8]            // 8-byte Folded Reload
	ldp	d9, d10, [sp, #16]      // 16-byte Folded Reload
	add	sp, sp, #32
	ret

Thanks,
-Hao

-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Wednesday, January 08, 2014 2:11 AM
To: reviews+D2438+public+f7effb52e6d4cbbc at llvm-reviews.chandlerc.com
Cc: Tim Northover; Hao Liu; Commit Messages and Patches for LLVM
Subject: Re: [PATCH] [AArch64] Add register spill code for large super
registers such as DPair, DTriple ...


On Jan 7, 2014, at 3:03 AM, Hao Liu <Hao.Liu at arm.com> wrote:

> 
>  As in the last commit I removed the code for spilling/filling D tuples, I
re-add D tuple spill/fill code again.
> 
>  There is still no test cases for D tuples, as the original test cases are
too large (hundreds of lines) and difficult to be simplified. The situation
of D tuples is similar to Q tuples, so we don't need to worry too much about
the correctness of D tuples.

You can use inline assembly to force spilling. See for example
test/CodeGen/Thumb2/aligned-spill.ll

Thanks,
/jakob