[PATCHES v5] [x86] 16-bit support

David Woodhouse dwmw2 at infradead.org
Tue Jan 7 17:44:19 PST 2014 

This is the current incarnation of code16 support. With the
corresponding patch to clang, I can now successfully build the 16-bit
boot code of the Linux kernel.

I only need to work around PR18415 (which bites on 32-bit too). I've
been looking at that but it seems beyond me; any assistance with that
would be appreciated.

The patches are attached, and also at
http://git.infradead.org/users/dwmw2/llvm.git

David Woodhouse (15):
      [x86] Add OpSize16 to instructions that need it
      [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode
      [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases
      [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases
      [x86] Disambiguate RET[QL] and fix aliases for 16-bit mode
      [x86] Fix JCXZ,JECXZ_32 for 16-bit mode
      [x86] Use 16-bit addressing where possible in 16-bit mode
      [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
      [x86] Make AsmParser validate registers for memory operands a bit better
      [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)
      [x86] Add JMP_2 and other 16-bit PC-relative branch instructions
      [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8
      [MC] Store MCCodeEmitter mode/feature flags in MCRelaxableFragment (PR18303)
      [x86] Propagate feature bits from X86MCCodeEmitter::EncodeInstruction()
      [x86] Add x86_16 target

I can commit these myself now, if anyone would care to approve them...

=========================
Version 5:

 - Add OpSize16 to a few more instructions that I'd missed the first time(s).

 - Expose MOV8ao8_16 in all modes, and fix the disassembler to cope with
   it this time instead of complaining about duplicates. And perhaps I
   really *do* need to add an AdSize16 bit to parallel OpSize16?

 - New version of PR18303 fix, which is now nearer the end of the series
   and split into two parts — the generic MC part, and the X86 part.

 - New patches: Fix for PR18414, make AsmParser catch more errors,
   support 8-bit and 16-bit relocations and 16-bit branches, and finally
   to add support the x86_16 target triple.

=========================
Version 4:

- User feedback found PR18303, which is now fixed in patch #2 of the
  series. I posted a couple of versions of this; this is the latest one
  which stores the current features bits in the MCRelaxableFragment as
  the instructions are first emitted, and then uses those features when
  subsequently re-encoding the instruction after relaxation. (As opposed
  to using the features that happen to be left active when the AsmParser
  finished parsing the file, which is the cause of the bug.)

- Use three separate feature bits for 16/32/64-bit mode instead of only
  16-bit and 64-bit flags.

- Patches attached instead of in mail thread, for the benefit of those
  whose mailers can't cope with threading.

=========================
Version 3:

- Be less taciturn in comments.

- Fix some indentation errors.

- Add test cases incrementally as things start to work.

- Drop the renaming of In32BitMode -> Not64BitMode since that was merged
  already in r197768... which also means we can:

- Subsume the addition of In32BitMode, In16BitMode and Not16BitMode into
  the patch which adds .code16 support, rather than having it separate.

- Drop rdar:// and PR comments from x86-16.s since they're pointless and
  Eric is apparently going to drop them from the x86-32 version too.

- Fix EH_RETURN/EH_RETURN64 handling to use is64BitMode() to choose
  between RETQ and RETL, like everything else in that patch did. There
  *may* be a potential micro-optimisation there, but it's probably not
  worth it. Eric made a cryptic comment about this patch which I also
  preserved for posterity, but I have no idea what it meant.

=========================
Version 2:

Dropped the reloc_signed_2byte patch since I don't think it was
necessary. Now it just uses FK_Data_2. We don't have a corresponding
signed relocation type anyway (in ELF at least).

Fixed more instructions to work correctly in 16-bit mode and added test
cases for it all (including some in .code32 for the 16-bit addressing
modes)

-- 
dwmw2
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