[Patch] [ThumbV8] Fix assertion fails due to inconsistent CPSR liveness of IT blocks

[Weiming Zhao]

Hi,

 

Attached patch fixes assertion fails due to inconsistent CPSR liveness of IT
blocks.

See bug http://llvm.org/bugs/show_bug.cgi?id=18369

 

The issue is caused when Post-RA scheduler reorders a bundle instruction (IT
block) and a vseleq. However, it only flips the CPSR liveness of the bundle
instruction, leaves the instructions inside the bundle unchanged, which
causes inconstancy.

 

This inconsistency causes Thumb2SizeReduction.cpp::ReduceMBB() crash because
CPSR is expected to be LIVE for VSELEQD.
 
There is a FIXME in Thumb2SizeReduction.cpp that tries to fixup such
inconsistency, but it seems incomplete. This patch augments the fixup.
Please help to review it.
 
Thanks,
Weiming

 

 

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