[llvm] r198359 - [PPC] Fix the scheduling of CR logicals on the P7

[Hal Finkel]

Author: hfinkel
Date: Thu Jan  2 15:38:26 2014
New Revision: 198359

URL: http://llvm.org/viewvc/llvm-project?rev=198359&view=rev
Log:
[PPC] Fix the scheduling of CR logicals on the P7

CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
    llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=198359&r1=198358&r2=198359&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Thu Jan  2 15:38:26 2014
@@ -128,6 +128,7 @@ bool PPCDispatchGroupSBHazardRecognizer:
   default:
     // All multi-slot instructions must come first.
     return NSlots > 1;
+  case PPC::Sched::IIC_BrCR: // cr logicals
   case PPC::Sched::IIC_SprMFCR:
   case PPC::Sched::IIC_SprMFCRF:
   case PPC::Sched::IIC_SprMTSPR:

Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td?rev=198359&r1=198358&r2=198359&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td Thu Jan  2 15:38:26 2014
@@ -137,8 +137,8 @@ def P7Itineraries : ProcessorItineraries
   InstrItinData<IIC_BrB         , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
                                    InstrStage<1, [P7_BRU]>],
                                   [3, 1, 1]>,
-  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
-                                   InstrStage<1, [P7_BRU]>],
+  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU1], 0>,
+                                   InstrStage<1, [P7_CRU]>],
                                   [3, 1, 1]>,
   InstrItinData<IIC_BrMCR       , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
                                    InstrStage<1, [P7_BRU]>],