[llvm] r198190 - Fix a bug in DAGcombiner about zero-extend after setcc.

[Kevin Qin]

Author: kevinqin
Date: Sun Dec 29 20:05:13 2013
New Revision: 198190

URL: http://llvm.org/viewvc/llvm-project?rev=198190&view=rev
Log:
Fix a bug in DAGcombiner about zero-extend after setcc.

For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/AArch64/neon-shift-left-long.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=198190&r1=198189&r2=198190&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Dec 29 20:05:13 2013
@@ -4970,7 +4970,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SD
   }
 
   if (N0.getOpcode() == ISD::SETCC) {
-    if (!LegalOperations && VT.isVector()) {
+    if (!LegalOperations && VT.isVector() &&
+        N0.getValueType().getVectorElementType() == MVT::i1) {
       // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
       // Only do this before legalize for now.
       EVT N0VT = N0.getOperand(0).getValueType();

Modified: llvm/trunk/test/CodeGen/AArch64/neon-shift-left-long.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-shift-left-long.ll?rev=198190&r1=198189&r2=198190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-shift-left-long.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-shift-left-long.ll Sun Dec 29 20:05:13 2013
@@ -191,3 +191,13 @@ define <2 x i64> @test_ushll2_shl0_v4i32
   %tmp = zext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %tmp
 }
+
+define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {
+; CHECK: test_ushll_cmp:
+; CHECK: cmeq	{{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK-NEXT: ushll	{{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+  %cmp.i = icmp eq <8 x i8> %a, %b
+  %vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>
+  %vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>
+  ret <8 x i16> %vmovl.i.i.i
+}