[llvm] r198125 - New machine model for cortex-a9. Schedule for resources and latency.

[Andrew Trick]

Author: atrick
Date: Sat Dec 28 15:57:05 2013
New Revision: 198125

URL: http://llvm.org/viewvc/llvm-project?rev=198125&view=rev
Log:
New machine model for cortex-a9. Schedule for resources and latency.

Schedule more conservatively to account for stalls on floating point
resources and latency. Use the AGU resource to model latency stalls
since it's shared between FP and LD/ST instructions. This might not be
completely accurate but should work well in practice.

Modified:
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
    llvm/trunk/test/CodeGen/ARM/saxpy10-a9.ll

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=198125&r1=198124&r2=198125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Sat Dec 28 15:57:05 2013
@@ -1902,14 +1902,20 @@ def CortexA9Model : SchedMachineModel {
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
+//
+// The AGU unit has BufferSize=1 so that the latency between operations
+// that use it are considered to stall other operations.
+//
+// The FP unit has BufferSize=0 so that it is a hard dispatch
+// hazard. No instruction may be dispatched while the unit is reserved.
 
 let SchedModel = CortexA9Model in {
 
 def A9UnitALU : ProcResource<2>;
 def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
-def A9UnitAGU : ProcResource<1>;
+def A9UnitAGU : ProcResource<1> { let BufferSize = 1; }
 def A9UnitLS  : ProcResource<1>;
-def A9UnitFP  : ProcResource<1> { let BufferSize = 1; }
+def A9UnitFP  : ProcResource<1> { let BufferSize = 0; }
 def A9UnitB   : ProcResource<1>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/ARM/saxpy10-a9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/saxpy10-a9.ll?rev=198125&r1=198124&r2=198125&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/saxpy10-a9.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/saxpy10-a9.ll Sat Dec 28 15:57:05 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false | FileCheck %s
+; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -misched-bench -scheditins=false | FileCheck %s
 ;
 ; Test MI-Sched suppory latency based stalls on in in-order pipeline
 ; using the new machine model.
@@ -15,43 +15,43 @@ target datalayout = "e-p:32:32:32-i1:8:3
 ; CHECK: vldr
 ; CHECK: vldr
 ; CHECK: vldr
-; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vldr
+; CHECK-NEXT: vldr
+; CHECK-NEXT: vadd
 ; CHECK-NEXT: vmul
+; CHECK-NEXT: vldr
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vadd
-; CHECK-NEXT: vldr
-; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
+; CHECK-NEXT: vldr
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
-; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
-; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
+; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
-; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
+; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
-; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
+; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
-; CHECK-NEXT: vadd
-; CHECK-NEXT: vldr
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
+; CHECK-NEXT: vldr
+; CHECK-NEXT: vmul
 ; CHECK-NEXT: vadd
 ; CHECK-NEXT: vldr
 ; CHECK-NEXT: vadd