[PATCH v2 11/14] [x86] Fix JCXZ,JECXZ_32 for 16-bit mode

[David Woodhouse]

JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that
appropriately conditional. And JECXZ needs the prefix instead.

We could have added an AdSize16 flag which parallels the OpSize16 flag.
Or we could do it this way, with a special case for the *one* instruction
that actually needs it. There seems to be precedent for such special cases,
so that seems like the simplest approach.
---
 lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 471a878..04669eb 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1145,7 +1145,8 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
 
   // Emit the address size opcode prefix as needed.
   bool need_address_override;
-  if (TSFlags & X86II::AdSize) {
+  if ((!is16BitMode() && TSFlags & X86II::AdSize) ||
+      (is16BitMode() && MI.getOpcode() == X86::JECXZ_32)) {
     need_address_override = true;
   } else if (MemOperand == -1) {
     need_address_override = false;
-- 
1.8.3.1


-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse at intel.com                              Intel Corporation
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