[PATCH v2 05/14] [x86] Add OpSize16 for instructions which need 0x66 prefix in 16-bit mode
David Woodhouse
dwmw2 at infradead.org
Wed Dec 18 10:09:21 PST 2013
---
lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 8 ++--
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 +-
lib/Target/X86/X86InstrFormats.td | 59 +++++++++++++-----------
3 files changed, 37 insertions(+), 33 deletions(-)
diff --git a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index 1ef9814..dcb9a8a 100644
--- a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -299,13 +299,15 @@ namespace X86II {
// OpSize - Set if this instruction requires an operand size prefix (0x66),
// which most often indicates that the instruction operates on 16 bit data
- // instead of 32 bit data.
+ // instead of 32 bit data. OpSize16 in 16 bit mode indicates that the
+ // instruction operates on 32 bit data instead of 16 bit data.
OpSize = 1 << 6,
+ OpSize16 = 1 << 7,
// AsSize - Set if this instruction requires an operand size prefix (0x67),
// which most often indicates that the instruction address 16 bit address
// instead of 32 bit address (or 32 bit address in 64 bit mode).
- AdSize = 1 << 7,
+ AdSize = 1 << 8,
//===------------------------------------------------------------------===//
// Op0Mask - There are several prefix bytes that are used to form two byte
@@ -313,7 +315,7 @@ namespace X86II {
// used to obtain the setting of this field. If no bits in this field is
// set, there is no prefix byte for obtaining a multibyte opcode.
//
- Op0Shift = 8,
+ Op0Shift = 9,
Op0Mask = 0x1F << Op0Shift,
// TB - TwoByte - Set if this instruction has a two byte opcode, which
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 1ce876b..471a878 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1166,8 +1166,7 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
EmitByte(0x67, CurByte, OS);
// Emit the operand size opcode prefix as needed.
- // FIXME for is16BitMode().
- if (TSFlags & X86II::OpSize)
+ if (TSFlags & (is16BitMode() ? X86II::OpSize16 : X86II::OpSize))
EmitByte(0x66, CurByte, OS);
bool Need0FPrefix = false;
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index 5022259..dc6273d 100644
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -113,6 +113,7 @@ def CD8VT8 : CD8VForm<7>; // v := 8
// Prefix byte classes which are used to indicate to the ad-hoc machine code
// emitter that various prefix bytes are required.
class OpSize { bit hasOpSizePrefix = 1; }
+class OpSize16 { bit hasOpSize16Prefix = 1; }
class AdSize { bit hasAdSizePrefix = 1; }
class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; }
@@ -187,8 +188,9 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
//
// Attributes specific to X86 instructions...
//
- bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
- bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
+ bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
+ bit hasOpSize16Prefix = 0; // Does this inst have a 0x66 prefix in 16-bit mode?
+ bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
bits<5> Prefix = 0; // Which prefix byte does this inst have?
bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
@@ -219,32 +221,33 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
// TSFlags layout should be kept in sync with X86InstrInfo.h.
let TSFlags{5-0} = FormBits;
let TSFlags{6} = hasOpSizePrefix;
- let TSFlags{7} = hasAdSizePrefix;
- let TSFlags{12-8} = Prefix;
- let TSFlags{13} = hasREX_WPrefix;
- let TSFlags{16-14} = ImmT.Value;
- let TSFlags{19-17} = FPForm.Value;
- let TSFlags{20} = hasLockPrefix;
- let TSFlags{22-21} = SegOvrBits;
- let TSFlags{24-23} = ExeDomain.Value;
- let TSFlags{32-25} = Opcode;
- let TSFlags{33} = hasVEXPrefix;
- let TSFlags{34} = hasVEX_WPrefix;
- let TSFlags{35} = hasVEX_4VPrefix;
- let TSFlags{36} = hasVEX_4VOp3Prefix;
- let TSFlags{37} = hasVEX_i8ImmReg;
- let TSFlags{38} = hasVEX_L;
- let TSFlags{39} = ignoresVEX_L;
- let TSFlags{40} = hasEVEXPrefix;
- let TSFlags{41} = hasEVEX_K;
- let TSFlags{42} = hasEVEX_Z;
- let TSFlags{43} = hasEVEX_L2;
- let TSFlags{44} = hasEVEX_B;
- let TSFlags{46-45} = EVEX_CD8E;
- let TSFlags{49-47} = EVEX_CD8V;
- let TSFlags{50} = has3DNow0F0FOpcode;
- let TSFlags{51} = hasMemOp4Prefix;
- let TSFlags{52} = hasXOP_Prefix;
+ let TSFlags{7} = hasOpSize16Prefix;
+ let TSFlags{8} = hasAdSizePrefix;
+ let TSFlags{13-9} = Prefix;
+ let TSFlags{14} = hasREX_WPrefix;
+ let TSFlags{17-15} = ImmT.Value;
+ let TSFlags{20-18} = FPForm.Value;
+ let TSFlags{21} = hasLockPrefix;
+ let TSFlags{23-22} = SegOvrBits;
+ let TSFlags{25-24} = ExeDomain.Value;
+ let TSFlags{33-26} = Opcode;
+ let TSFlags{34} = hasVEXPrefix;
+ let TSFlags{35} = hasVEX_WPrefix;
+ let TSFlags{36} = hasVEX_4VPrefix;
+ let TSFlags{37} = hasVEX_4VOp3Prefix;
+ let TSFlags{38} = hasVEX_i8ImmReg;
+ let TSFlags{39} = hasVEX_L;
+ let TSFlags{40} = ignoresVEX_L;
+ let TSFlags{41} = hasEVEXPrefix;
+ let TSFlags{42} = hasEVEX_K;
+ let TSFlags{43} = hasEVEX_Z;
+ let TSFlags{44} = hasEVEX_L2;
+ let TSFlags{45} = hasEVEX_B;
+ let TSFlags{47-46} = EVEX_CD8E;
+ let TSFlags{50-48} = EVEX_CD8V;
+ let TSFlags{51} = has3DNow0F0FOpcode;
+ let TSFlags{52} = hasMemOp4Prefix;
+ let TSFlags{53} = hasXOP_Prefix;
}
class PseudoI<dag oops, dag iops, list<dag> pattern>
--
1.8.3.1
--
David Woodhouse Open Source Technology Centre
David.Woodhouse at intel.com Intel Corporation
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