[llvm] r197572 - One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.

[Rafael Espindola]

Author: rafael
Date: Wed Dec 18 08:35:37 2013
New Revision: 197572

URL: http://llvm.org/viewvc/llvm-project?rev=197572&view=rev
Log:
One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.

Thanks for Iain Sandoe for testing this with the original gcc.

Clang was already getting this right.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
    llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=197572&r1=197571&r2=197572&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Dec 18 08:35:37 2013
@@ -47,7 +47,8 @@ static std::string getDataLayoutString(c
 
   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
   // documentation are wrong; these are correct (i.e. "what gcc does").
-  Ret += "-i64:64";
+  if (ST.isPPC64() || ST.isSVR4ABI())
+    Ret += "-i64:64";
 
   // Set support for 128 floats depending on the ABI.
   if (!ST.isPPC64() || !ST.isSVR4ABI())

Modified: llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll?rev=197572&r1=197571&r2=197572&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll Wed Dec 18 08:35:37 2013
@@ -119,9 +119,9 @@ unequal:
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
 ; DARWIN32: _func3:
-; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 40
+; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
 ; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
-; DARWIN32: lwz r[[REG3:[0-9]+]], 48(r[[REGSP]])
+; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
 ; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]