[RFC PATCH 1/1] R600: Allow ftrunc

[Tom Stellard]

On Tue, Dec 17, 2013 at 01:24:32PM -0500, Jan Vesely wrote:
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
> Hi,
> 
> I used CEIL as a template to add TRUNC functionality.
> I only found ISA documentation for r700 hw, and it does not mention how trunc
> instruction behaves for negative numbers.
> This patch (together with a patch I sent earlier to libclc) makes
> gegl 'posterize' test pass on my AMD Turks (with few workarounds for
> other issues).
> 

You can find all the ISA documents for AMD GPUs here:
http://www.x.org/docs/AMD/

> regards,
> Jan
> 
> PS: please keep me in cc, I'm not subscribed to the list
> 
>  lib/Target/R600/AMDGPUISelLowering.cpp | 2 ++
>  lib/Target/R600/R600Instructions.td    | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
> index d7ee8e6..c59be7c 100644
> --- a/lib/Target/R600/AMDGPUISelLowering.cpp
> +++ b/lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -60,6 +60,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
>    setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
>    setOperationAction(ISD::FRINT,  MVT::f32, Legal);
>    setOperationAction(ISD::FROUND, MVT::f32, Legal);
> +  setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
>  
>    // The hardware supports ROTR, but not ROTL
>    setOperationAction(ISD::ROTL, MVT::i32, Expand);
> @@ -184,6 +185,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
>      setOperationAction(ISD::FADD, VT, Expand);
>      setOperationAction(ISD::FDIV, VT, Expand);
>      setOperationAction(ISD::FFLOOR, VT, Expand);
> +    setOperationAction(ISD::FTRUNC, VT, Expand);
>      setOperationAction(ISD::FMUL, VT, Expand);
>      setOperationAction(ISD::FRINT, VT, Expand);
>      setOperationAction(ISD::FSQRT, VT, Expand);
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 2249cee..97969e9 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -728,7 +728,7 @@ def SETNE_DX10 : R600_2OP <
>  >;
>  
>  def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
> -def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
> +def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>;

We use the llvm.AMDGPU.trunc intrinsic in Mesa for GLSL (We should
probably replace this with ftrunc to be consistent, but this is a
separate issue), so this change will break Mesa.

You will need to add ftrunc lowering as a stand-alone pattern.
Something like:

def : Pat <
   (ftrunc f32:$src0),
   (TRUNC $src0)
>;

There are a few examples of patterns like this at the bottom of
R600Instructions.td and also AMDGPUInstructions.td.

-Tom

>  def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
>  def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
>  def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
> -- 
> 1.8.3.1
> 
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