[llvm] r197514 - Disabled subregister copy coalescing during MachineCSE.

[Andrew Trick]

Author: atrick
Date: Tue Dec 17 13:29:36 2013
New Revision: 197514

URL: http://llvm.org/viewvc/llvm-project?rev=197514&view=rev
Log:
Disabled subregister copy coalescing during MachineCSE.

This effectively backs out r197465 but leaves some of the general
fixes in place. Not all targets are ready to handle this feature. To
enable it, some infrastructure work is needed to better handle
register class constraints.

Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/test/CodeGen/X86/cmov.ll
    llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=197514&r1=197513&r2=197514&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Dec 17 13:29:36 2013
@@ -133,16 +133,26 @@ bool MachineCSE::PerformTrivialCoalescin
       continue;
     if (DefMI->getOperand(0).getSubReg())
       continue;
-    unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
+    // FIXME: We should trivially coalesce subregister copies to expose CSE
+    // opportunities on instructions with truncated operands (see
+    // cse-add-with-overflow.ll). This can be done here as follows:
+    // if (SrcSubReg)
+    //  RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
+    //                                     SrcSubReg);
+    // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+    //
+    // The 2-addr pass has been updated to handle coalesced subregs. However,
+    // some machine-specific code still can't handle it.
+    // To handle it properly we also need a way find a constrained subregister
+    // class given a super-reg class and subreg index.
+    if (DefMI->getOperand(1).getSubReg())
+      continue;
     const TargetRegisterClass *RC = MRI->getRegClass(Reg);
-    if (SrcSubReg)
-      RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
-                                         SrcSubReg);
     if (!MRI->constrainRegClass(SrcReg, RC))
       continue;
     DEBUG(dbgs() << "Coalescing: " << *DefMI);
     DEBUG(dbgs() << "***     to: " << *MI);
-    MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+    MO.setReg(SrcReg);
     MRI->clearKillFlags(SrcReg);
     DefMI->eraseFromParent();
     ++NumCoalesces;

Modified: llvm/trunk/test/CodeGen/X86/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=197514&r1=197513&r2=197514&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov.ll Tue Dec 17 13:29:36 2013
@@ -42,7 +42,7 @@ declare void @bar(i64) nounwind
 define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:      cmov{{n?}}el %[[R1:e..]], %[[R2:e..]]
-; CHECK-NEXT: movl    %[[R2]], %[[R2]]
+; CHECK-NEXT: movl    %[[R2]], %{{e..}}
 
   %c = trunc i64 %a to i32
   %d = trunc i64 %b to i32

Modified: llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll?rev=197514&r1=197513&r2=197514&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll Tue Dec 17 13:29:36 2013
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=generic | FileCheck %s
+; XFAIL: *
 ; rdar:15661073 simple example of redundant adds
 ;
 ; MachineCSE should coalesce trivial subregister copies.