[llvm] r197424 - Revert "Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies."
Rafael Espindola
rafael.espindola at gmail.com
Mon Dec 16 12:57:09 PST 2013
Author: rafael
Date: Mon Dec 16 14:57:09 2013
New Revision: 197424
URL: http://llvm.org/viewvc/llvm-project?rev=197424&view=rev
Log:
Revert "Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies."
This reverts commit r197414.
It broke the ppc64 bootstrap. I will post a testcase in a sec.
Removed:
llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll
Modified:
llvm/trunk/lib/CodeGen/MachineCSE.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/test/CodeGen/X86/cmov.ll
Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=197424&r1=197423&r2=197424&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Mon Dec 16 14:57:09 2013
@@ -131,18 +131,13 @@ bool MachineCSE::PerformTrivialCoalescin
unsigned SrcReg = DefMI->getOperand(1).getReg();
if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
continue;
- if (DefMI->getOperand(0).getSubReg())
+ if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
continue;
- unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
- const TargetRegisterClass *RC = MRI->getRegClass(Reg);
- if (SrcSubReg)
- RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
- SrcSubReg);
- if (!MRI->constrainRegClass(SrcReg, RC))
+ if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
continue;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << *MI);
- MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+ MO.setReg(SrcReg);
MRI->clearKillFlags(SrcReg);
DefMI->eraseFromParent();
++NumCoalesces;
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=197424&r1=197423&r2=197424&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Dec 16 14:57:09 2013
@@ -1349,7 +1349,6 @@ TwoAddressInstructionPass::processTiedPa
unsigned LastCopiedReg = 0;
SlotIndex LastCopyIdx;
unsigned RegB = 0;
- unsigned SubRegB = 0;
for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
unsigned SrcIdx = TiedPairs[tpi].first;
unsigned DstIdx = TiedPairs[tpi].second;
@@ -1360,7 +1359,6 @@ TwoAddressInstructionPass::processTiedPa
// Grab RegB from the instruction because it may have changed if the
// instruction was commuted.
RegB = MI->getOperand(SrcIdx).getReg();
- SubRegB = MI->getOperand(SrcIdx).getSubReg();
if (RegA == RegB) {
// The register is tied to multiple destinations (or else we would
@@ -1385,25 +1383,8 @@ TwoAddressInstructionPass::processTiedPa
#endif
// Emit a copy.
- MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
- TII->get(TargetOpcode::COPY), RegA);
- // If this operand is folding a truncation, the truncation now moves to the
- // copy so that the register classes remain valid for the operands.
- MIB.addReg(RegB, 0, SubRegB);
- const TargetRegisterClass *RC = MRI->getRegClass(RegB);
- if (SubRegB) {
- if (TargetRegisterInfo::isVirtualRegister(RegA)) {
- assert(TRI->getMatchingSuperRegClass(MRI->getRegClass(RegB),
- MRI->getRegClass(RegA), SubRegB) &&
- "tied subregister must be a truncation");
- // The superreg class will not be used to constrain the subreg class.
- RC = 0;
- }
- else {
- assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
- && "tied subregister must be a truncation");
- }
- }
+ BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
+ TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
// Update DistanceMap.
MachineBasicBlock::iterator PrevMI = MI;
@@ -1423,7 +1404,7 @@ TwoAddressInstructionPass::processTiedPa
}
}
- DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
+ DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
MachineOperand &MO = MI->getOperand(SrcIdx);
assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
@@ -1436,9 +1417,9 @@ TwoAddressInstructionPass::processTiedPa
// Make sure regA is a legal regclass for the SrcIdx operand.
if (TargetRegisterInfo::isVirtualRegister(RegA) &&
TargetRegisterInfo::isVirtualRegister(RegB))
- MRI->constrainRegClass(RegA, RC);
+ MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
+
MO.setReg(RegA);
- MO.setSubReg(0);
// Propagate SrcRegMap.
SrcRegMap[RegA] = RegB;
@@ -1450,14 +1431,12 @@ TwoAddressInstructionPass::processTiedPa
// Replace other (un-tied) uses of regB with LastCopiedReg.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
- MO.isUse()) {
+ if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
if (MO.isKill()) {
MO.setIsKill(false);
RemovedKillFlag = true;
}
MO.setReg(LastCopiedReg);
- MO.setSubReg(0);
}
}
}
Modified: llvm/trunk/test/CodeGen/X86/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=197424&r1=197423&r2=197424&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov.ll Mon Dec 16 14:57:09 2013
@@ -41,8 +41,8 @@ declare void @bar(i64) nounwind
define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
; CHECK-LABEL: test3:
-; CHECK: cmov{{n?}}el %[[R1:e..]], %[[R2:e..]]
-; CHECK-NEXT: movl %[[R2]], %[[R2]]
+; CHECK: cmovnel %edi, %esi
+; CHECK-NEXT: movl %esi, %edi
%c = trunc i64 %a to i32
%d = trunc i64 %b to i32
Removed: llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll?rev=197423&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cse-add-with-overflow.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=generic | FileCheck %s
-; rdar:15661073 simple example of redundant adds
-;
-; MachineCSE should coalesce trivial subregister copies.
-;
-; The extra movl+addl should be removed during MachineCSE.
-; CHECK-LABEL: redundantadd
-; CHECK: cmpq
-; CHECK: movq
-; CHECK-NOT: movl
-; CHECK: addl
-; CHECK-NOT: addl
-; CHECK: ret
-
-define i64 @redundantadd(i64* %a0, i64* %a1) {
-entry:
- %tmp8 = load i64* %a0, align 8
- %tmp12 = load i64* %a1, align 8
- %tmp13 = icmp ult i64 %tmp12, -281474976710656
- br i1 %tmp13, label %exit1, label %body
-
-exit1:
- unreachable
-
-body:
- %tmp14 = trunc i64 %tmp8 to i32
- %tmp15 = trunc i64 %tmp12 to i32
- %tmp16 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %tmp14, i32 %tmp15)
- %tmp17 = extractvalue { i32, i1 } %tmp16, 1
- br i1 %tmp17, label %exit2, label %return
-
-exit2:
- unreachable
-
-return:
- %tmp18 = add i64 %tmp12, %tmp8
- %tmp19 = and i64 %tmp18, 4294967295
- %tmp20 = or i64 %tmp19, -281474976710656
- ret i64 %tmp20
-}
-
-declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
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