[llvm] r197097 - Fix an over-constrained assertion in MachineFunction::addLiveIn.

[Quentin Colombet]

Author: qcolombet
Date: Wed Dec 11 18:15:47 2013
New Revision: 197097

URL: http://llvm.org/viewvc/llvm-project?rev=197097&view=rev
Log:
Fix an over-constrained assertion in MachineFunction::addLiveIn.
The assertion was checking that the virtual register VReg used to represent the
physical register PReg uses the same register class as the one passed to
MachineFunction::addLiveIn.
This is over-constraining because it is sufficient to check that the register
class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and
that VRegRC contains PReg.
Indeed, if VReg gets constrained because of some operation constraints
between two calls of MachineFunction::addLiveIn, the original assertion
cannot match.

This fixes <rdar://problem/15633429>. 

Added:
    llvm/trunk/test/CodeGen/AArch64/assertion-rc-mismatch.ll
Modified:
    llvm/trunk/lib/CodeGen/MachineFunction.cpp

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=197097&r1=197096&r2=197097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Wed Dec 11 18:15:47 2013
@@ -425,7 +425,16 @@ unsigned MachineFunction::addLiveIn(unsi
   MachineRegisterInfo &MRI = getRegInfo();
   unsigned VReg = MRI.getLiveInVirtReg(PReg);
   if (VReg) {
-    assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
+    const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
+    (void)VRegRC;
+    // A physical register can be added several times.
+    // Between two calls, the register class of the related virtual register
+    // may have been constrained to match some operation constraints.
+    // In that case, check that the current register class includes the
+    // physical register and is a sub class of the specified RC.
+    assert((VRegRC == RC || (VRegRC->contains(PReg) &&
+                             RC->hasSubClassEq(VRegRC))) &&
+            "Register class mismatch!");
     return VReg;
   }
   VReg = MRI.createVirtualRegister(RC);

Added: llvm/trunk/test/CodeGen/AArch64/assertion-rc-mismatch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/assertion-rc-mismatch.ll?rev=197097&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/assertion-rc-mismatch.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/assertion-rc-mismatch.ll Wed Dec 11 18:15:47 2013
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; Test case related to <rdar://problem/15633429>.
+
+; CHECK-LABEL: small
+define i64 @small(i64 %encodedBase) {
+cmp:
+  %lnot.i.i = icmp eq i64 %encodedBase, 0
+  br i1 %lnot.i.i, label %if, label %else
+if:
+  %tmp1 = call i8* @llvm.returnaddress(i32 0)
+  br label %end
+else:
+  %tmp3 = call i8* @llvm.returnaddress(i32 0)
+  %ptr = getelementptr inbounds i8* %tmp3, i64 -16
+  %ld = load i8* %ptr, align 4
+  %tmp2 = inttoptr i8 %ld to i8*
+  br label %end
+end:
+  %tmp = phi i8* [ %tmp1, %if ], [ %tmp2, %else ]
+  %coerce.val.pi56 = ptrtoint i8* %tmp to i64
+  ret i64 %coerce.val.pi56
+}
+
+declare i8* @llvm.returnaddress(i32)