[www] r196980 - Links to lightning talk slides.

[Tanya Lattner]

Author: tbrethou
Date: Tue Dec 10 16:49:40 2013
New Revision: 196980

URL: http://llvm.org/viewvc/llvm-project?rev=196980&view=rev
Log:
Links to lightning talk slides.

Modified:
    www/trunk/devmtg/2013-11/index.html

Modified: www/trunk/devmtg/2013-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2013-11/index.html?rev=196980&r1=196979&r2=196980&view=diff
==============================================================================
--- www/trunk/devmtg/2013-11/index.html (original)
+++ www/trunk/devmtg/2013-11/index.html Tue Dec 10 16:49:40 2013
@@ -280,24 +280,28 @@ Automatic differentiation (AD) evaluates
 <p>
 <b>Fixing MC for ARM v7-A: Just a few corner cases – how hard can it be?</b><br>
 <i>Mihail Popa - ARM</i><br>
+<a href="slides/Popa-MCARM.pdf">Slides</a><br>
 In 2012, MC Hammer was presented as a testing infrastructure to exhaustively verify the MC layer implementation for the ARM backend. Within ARM we have been working to fix any bugs and we have reached the point where all but one problem remains unsolved.  Some of the issues discovered in this process have proven to be excessively difficult to fix. The purpose of the presentation is to give a brief rundown of the major headaches and to suggest possible courses of action for improving LLVM infrastructure.
 </p>
 
 <p>
 <b>VLIW Support in the MC Layer</b><br>
 <i>Mario Guerra - Qualcomm Innovation Center, Incorporated</i><br>
+<a href="slides/Guerra-VLIW.pdf">Slides</a><br>
 Modern DSP architectures such as Hexagon use VLIW instruction packets, which are not well suited to the single instruction streaming model of the LLVM MC layer. Developing an assembler for Hexagon presents unique challenges in the MC layer, especially since Hexagon leverages an optimizing assembler to achieve maximum performance. It is possible to support VLIW within the MC layer by treating every MC instruction as a bundle, and adding all instructions in a packet as sub instruction operands. Furthermore, subclassing MCInst to create a target-specific type of MCInst allows us to capture packet information that will be used to make optimization decisions prior to emitting the code to object format. 
 </p>
 
 <p>
 <b>Link-Time Optimization without Linker Support</b><br>
 <i>Yunzhong Gao - Sony Computer Entertainment America</i><br>
- LLVM's plugin for the Gold linker enables link-time optimization (LTO).  But the toolchain for PlayStation®4 does not include Gold.  Here's how we achieved LTO without a bitcode-aware linker.
+<a href="slides/Gao-LTO.pdf">Slides</a><br>
+LLVM's plugin for the Gold linker enables link-time optimization (LTO).  But the toolchain for PlayStation®4 does not include Gold.  Here's how we achieved LTO without a bitcode-aware linker.
 </p>
 
 <p>
 <b>A comparison of the DWARF debugging information produced by LLVM and GCC</b><br>
 <i>Keith Walker, ARM</i><br>
+<a href="slides/Walker-DWARF.pdf">Slides</a><br>
 This talk explores the quality of the DWARF debugging information generated by LLVM by
 comparing it with that produced by GCC for ARM/AArch64 based targets. It highlights where LLVM's debugging information is superior to that generated by GCC
 and also where there are deficiencies and scope for further development.
@@ -308,24 +312,27 @@ for users of LLVM.
 <p>
 <b>aarch64 neon work</b><br>
 <i>Ana Pazos - QuIC, Jiangning Liu - ARM </i><br>
-ARM and Qualcom are implementing aarch64 advanced SIMD (neon) instruction set. We as a joint team will be implementing all of 25 classes of neon instructions on MC layer as well as all of ACLE(ARM C Language Extension) intrinsics on C level. Our talk will highlight the design choice of unique arm_neon.h for both ARM(aarch32) and aarch64, appropriate decision making of value types on LLVM IR for generating SISD instruction classes, the patterns’ qualities in .td files by reducing LLVM IR intrinsics, and all of the test categories to build a robust back-end. Finally, we’d like to mention some future plan like enabling machine instruction based scheduler, and performance tuning etc.        
+<a href="slides/Pazos-Aarch64.pdf">Slides</a><br>ARM and Qualcom are implementing aarch64 advanced SIMD (neon) instruction set. We as a joint team will be implementing all of 25 classes of neon instructions on MC layer as well as all of ACLE(ARM C Language Extension) intrinsics on C level. Our talk will highlight the design choice of unique arm_neon.h for both ARM(aarch32) and aarch64, appropriate decision making of value types on LLVM IR for generating SISD instruction classes, the patterns’ qualities in .td files by reducing LLVM IR intrinsics, and all of the test categories to build a robust back-end. Finally, we’d like to mention some future plan like enabling machine instruction based scheduler, and performance tuning etc.        
 </p>
 
 <p>
 <b>JavaScript JIT with LLVM</b><br>
 <i>Filip Pizlo - Apple Inc.</i><br>
+<a href="slides/Pizlo-JavascriptJIT.pdf">Slides</a><br>
 Dynamic languages present unique challenges for compilation, such as the need for type speculation and self-modifying code.  This talk shows how to add support for these features to LLVM and use them to implement a JIT for JavaScript.
 </p>
 
 <p>
 <b>Debug Info Quick Update</b><br>
 <i>Eric Christopher - Google Inc.</i><br>
+<a href="slides/Christopher-DebugInfo.pdf">Slides</a><br>
 A quick update on what's been going on in debug info support since the Euro meeting.         
 </p>
 
 <p>
 <b>lld a linker framework</b><br>
 <i>Shankar Easwaran, Qualcomm Innovation Centre.</i><br>
+<a href="slides/Easwaran-LLD.pdf">Slides</a><br>
 The lld project is working towards becoming a production quality linker targeting PECOFF, Darwin, ELF formats.The lld project is under heavy development. The talk discusses on how lld achieves universal linking and how its moving towards becoming a linker framework that could be an integral part of llvm. The talk continues to discuss by exposes new opportunities with linking like, lld API's, Symbol resolution improvements, Link time optimizations(LTO) and enhancing the user experience by providing diagnostics, user driven inputs that drive linker behavior.
 </p>