[llvm] r196971 - Use llvm_unreachable instead of assert(0)
Matt Arsenault
Matthew.Arsenault at amd.com
Tue Dec 10 13:37:42 PST 2013
Author: arsenm
Date: Tue Dec 10 15:37:42 2013
New Revision: 196971
URL: http://llvm.org/viewvc/llvm-project?rev=196971&view=rev
Log:
Use llvm_unreachable instead of assert(0)
Modified:
llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp
llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp
llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp
llvm/trunk/lib/Target/R600/SIAnnotateControlFlow.cpp
llvm/trunk/lib/Target/R600/SIInstrInfo.h
llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp
Modified: llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUAsmPrinter.cpp Tue Dec 10 15:37:42 2013
@@ -257,7 +257,7 @@ void AMDGPUAsmPrinter::findNumUsedRegist
isSGPR = false;
width = 16;
} else {
- assert(!"Unknown register class");
+ llvm_unreachable("Unknown register class");
}
hwReg = RI->getEncodingValue(reg) & 0xff;
maxUsed = hwReg + width - 1;
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Tue Dec 10 15:37:42 2013
@@ -254,8 +254,8 @@ SDValue AMDGPUTargetLowering::LowerOpera
switch (Op.getOpcode()) {
default:
Op.getNode()->dump();
- assert(0 && "Custom lowering code for this"
- "instruction is not implemented yet!");
+ llvm_unreachable("Custom lowering code for this"
+ "instruction is not implemented yet!");
break;
// AMDIL DAG lowering
case ISD::SDIV: return LowerSDIV(Op, DAG);
@@ -455,7 +455,7 @@ SDValue AMDGPUTargetLowering::LowerMinMa
case ISD::SETTRUE2:
case ISD::SETUO:
case ISD::SETO:
- assert(0 && "Operation should already be optimised !");
+ llvm_unreachable("Operation should already be optimised!");
case ISD::SETULE:
case ISD::SETULT:
case ISD::SETOLE:
@@ -479,7 +479,7 @@ SDValue AMDGPUTargetLowering::LowerMinMa
return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
}
case ISD::SETCC_INVALID:
- assert(0 && "Invalid setcc condcode !");
+ llvm_unreachable("Invalid setcc condcode!");
}
return Op;
}
Modified: llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.cpp Tue Dec 10 15:37:42 2013
@@ -110,7 +110,7 @@ AMDGPUInstrInfo::storeRegToStackSlot(Mac
int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- assert(!"Not Implemented");
+ llvm_unreachable("Not Implemented");
}
void
@@ -119,7 +119,7 @@ AMDGPUInstrInfo::loadRegFromStackSlot(Ma
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- assert(!"Not Implemented");
+ llvm_unreachable("Not Implemented");
}
bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
Modified: llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPURegisterInfo.cpp Tue Dec 10 15:37:42 2013
@@ -38,7 +38,7 @@ void AMDGPURegisterInfo::eliminateFrameI
int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const {
- assert(!"Subroutines not supported yet");
+ llvm_unreachable("Subroutines not supported yet");
}
unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Tue Dec 10 15:37:42 2013
@@ -977,7 +977,7 @@ SDValue R600TargetLowering::LowerSELECT_
HWFalse = DAG.getConstant(0, CompareVT);
}
else {
- assert(!"Unhandled value type in LowerSELECT_CC");
+ llvm_unreachable("Unhandled value type in LowerSELECT_CC");
}
// Lower this unsupported SELECT_CC into a combination of two supported
@@ -1099,7 +1099,7 @@ SDValue R600TargetLowering::LowerSTORE(S
Ptr, DAG.getConstant(2, MVT::i32)));
if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
- assert(!"Truncated and indexed stores not supported yet");
+ llvm_unreachable("Truncated and indexed stores not supported yet");
} else {
Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
}
Modified: llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp Tue Dec 10 15:37:42 2013
@@ -63,7 +63,7 @@ public:
DenseMap<unsigned, unsigned> RegToChan;
std::vector<unsigned> UndefReg;
RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
- assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
+ assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
MachineOperand &MO = Instr->getOperand(i);
unsigned Chan = Instr->getOperand(i + 1).getImm();
Modified: llvm/trunk/lib/Target/R600/SIAnnotateControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIAnnotateControlFlow.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIAnnotateControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIAnnotateControlFlow.cpp Tue Dec 10 15:37:42 2013
@@ -253,7 +253,7 @@ void SIAnnotateControlFlow::handleLoopCo
PhiInserter.AddAvailableValue(Parent, Ret);
} else {
- assert(0 && "Unhandled loop condition!");
+ llvm_unreachable("Unhandled loop condition!");
}
}
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.h?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.h Tue Dec 10 15:37:42 2013
@@ -60,7 +60,10 @@ public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI=false) const;
- virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
+ virtual unsigned getIEQOpcode() const {
+ llvm_unreachable("Unimplemented");
+ }
+
MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned DstReg, unsigned SrcReg) const;
Modified: llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp?rev=196971&r1=196970&r2=196971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp Tue Dec 10 15:37:42 2013
@@ -283,16 +283,11 @@ void SILowerControlFlowPass::EndCf(Machi
}
void SILowerControlFlowPass::Branch(MachineInstr &MI) {
- MachineBasicBlock *Next = MI.getParent()->getNextNode();
- MachineBasicBlock *Target = MI.getOperand(0).getMBB();
- if (Target == Next)
- MI.eraseFromParent();
- else
- assert(0);
+ assert(MI.getOperand(0).getMBB() == MI.getParent()->getNextNode());
+ MI.eraseFromParent();
}
void SILowerControlFlowPass::Kill(MachineInstr &MI) {
-
MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = MI.getDebugLoc();
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