[PATCH][X86] Fix for a a poor code generation bug affecting addss/mulss and other SSE scalar fp arithmetic instructions
Andrea Di Biagio
andrea.dibiagio at gmail.com
Mon Dec 9 12:53:35 PST 2013
Sorry for sending a new patch, however I just realized that my last
patch could be improved introducing more generic patterns to also
match the case where not all the operands of a scalar floating point
arithmetic instruction are generated by a 'extract_vector_elt'.
Example:
define <4 x float> @foo(<4 x float> %a, <4 x float> %b) {
%1 = extractelement <4 x float> %b, i32 0
%2 = extractelement <4 x float> %a, i32 0
%3 = fadd float %1, %2
%4 = fadd float %2, %3
%result = insertelement <4 x float> %a, %4, i32 0
}
Should generate:
addss %xmm0, %xmm1
addss %xmm1, %xmm0
ret
The new patch in attachment introduces more test cases and also adds
explicit CHECK-NOT to verify that we don't generate redundant inserts.
Please let me know what do you think.
Thanks,
Andrea Di Biagio
On Mon, Dec 9, 2013 at 3:35 PM, Andrea Di Biagio
<andrea.dibiagio at gmail.com> wrote:
> Hi Jim,
> I fixed the problem as you suggested by simply adding new patterns
> and I have attached a new version of the patch.
> Please let me know what do you think and if it is ok to submit.
>
> Thanks,
> Andrea Di Biagio
>
>
> On Sat, Dec 7, 2013 at 10:31 AM, Andrea Di Biagio
> <andrea.dibiagio at gmail.com> wrote:
>> Hi Jim,
>>
>> Thanks for the feedback!
>> I understand your concerns and I agree that adding new target ISD
>> nodes is not ideal.
>> I'll try to fix the problem as you suggested by simply adding new
>> patterns in X86InstrSSE.td and I'll send a new patch for review.
>>
>> Thanks,
>> Andrea
>>
>> On Fri, Dec 6, 2013 at 11:52 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>> It won’t work to just recognize the insert directly in the patterns and avoid the DAGcombine entirely? I’d prefer to avoid adding extra target ISD nodes if we can help it. They inhibit optimization (other DAGcombines) and make other codegen patterns harder to generalize.
>>>
>>> -Jim
>>>
>>> On Dec 6, 2013, at 1:40 PM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote:
>>>
>>>> Hi,
>>>>
>>>> This patch fixes a poor code generation bug affecting SSE scalar fp
>>>> instructions like addss/mulss.
>>>> The problem has been originally reported here:
>>>> http://comments.gmane.org/gmane.comp.compilers.llvm.devel/68542
>>>>
>>>> At the moment, the x86 backend tends to emit unnecessary vector insert
>>>> instructions immediately after sse scalar fp instructions.
>>>>
>>>> Example:
>>>> /////////////////////////////////
>>>> __m128 foo(__m128 A, __m128 B) {
>>>> A[0] += B[0];
>>>> return A;
>>>> }
>>>> /////////////////////////////////
>>>>
>>>> produces the following sequence:
>>>> addss %xmm0, %xmm1
>>>> movss %xmm1, %xmm0
>>>>
>>>> Instead of:
>>>> addss %xmm1, %xmm0
>>>>
>>>> This patch addresses the problem at ISel stage introducing a target
>>>> specific combine rule to fold patterns like this one:
>>>>
>>>> a0 : f32 = extract_vector_elt ( A, 0)
>>>> b0 : f32 = extract_vector_elt ( B, 0)
>>>> r0 : f32 = fadd a0, b0
>>>> result : v4f32 = insert_vector_elt ( A, r0, 0 )
>>>>
>>>> into a single 'addss' instruction.
>>>>
>>>> Please let me know what you think.
>>>>
>>>> Thanks,
>>>> Andrea Di Biagio
>>>> SN Systems - Sony Computer Entertainment Group
>>>> <patch.diff>_______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
-------------- next part --------------
Index: lib/Target/X86/X86InstrSSE.td
===================================================================
--- lib/Target/X86/X86InstrSSE.td (revision 196812)
+++ lib/Target/X86/X86InstrSSE.td (working copy)
@@ -3017,6 +3017,96 @@
basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
}
+def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
+ (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))))),
+ (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
+ (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))))),
+ (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
+ (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))))),
+ (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
+ (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))))),
+ (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+
+let Predicates = [HasSSE2] in {
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+}
+
+let Predicates = [UseSSE41] in {
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+}
+
+let AddedComplexity = 20, Predicates = [HasAVX] in {
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
+ (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
+ FR64:$src))))),
+ (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+ def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
+ (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
+ FR32:$src))), (iPTR 0))),
+ (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
+}
+
/// Unop Arithmetic
/// In addition, we also have a special variant of the scalar form here to
/// represent the associated intrinsic operation. This form is unlike the
Index: test/CodeGen/X86/sse-scalar-fp-arith.ll
===================================================================
--- test/CodeGen/X86/sse-scalar-fp-arith.ll (revision 0)
+++ test/CodeGen/X86/sse-scalar-fp-arith.ll (revision 0)
@@ -0,0 +1,305 @@
+; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
+; RUN: llc -mtriple=x86_64-pc-linux -mattr=-sse4.1 -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
+; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7-avx < %s | FileCheck -check-prefix=CHECK -check-prefix=AVX %s
+
+define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %add = fadd float %2, %1
+ %3 = insertelement <4 x float> %a, float %add, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_add_ss
+; SSE2: addss %xmm1, %xmm0
+; AVX: vaddss %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %sub = fsub float %2, %1
+ %3 = insertelement <4 x float> %a, float %sub, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_sub_ss
+; SSE2: subss %xmm1, %xmm0
+; AVX: vsubss %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %mul = fmul float %2, %1
+ %3 = insertelement <4 x float> %a, float %mul, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_mul_ss
+; SSE2: mulss %xmm1, %xmm0
+; AVX: vmulss %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %div = fdiv float %2, %1
+ %3 = insertelement <4 x float> %a, float %div, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_div_ss
+; SSE2: divss %xmm1, %xmm0
+; AVX: vdivss %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %b, i32 0
+ %2 = extractelement <2 x double> %a, i32 0
+ %add = fadd double %2, %1
+ %3 = insertelement <2 x double> %a, double %add, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_add_sd
+; SSE2: addsd %xmm1, %xmm0
+; AVX: vaddsd %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %b, i32 0
+ %2 = extractelement <2 x double> %a, i32 0
+ %sub = fsub double %2, %1
+ %3 = insertelement <2 x double> %a, double %sub, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_sub_sd
+; SSE2: subsd %xmm1, %xmm0
+; AVX: vsubsd %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %b, i32 0
+ %2 = extractelement <2 x double> %a, i32 0
+ %mul = fmul double %2, %1
+ %3 = insertelement <2 x double> %a, double %mul, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_mul_sd
+; SSE2: mulsd %xmm1, %xmm0
+; AVX: vmulsd %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %b, i32 0
+ %2 = extractelement <2 x double> %a, i32 0
+ %div = fdiv double %2, %1
+ %3 = insertelement <2 x double> %a, double %div, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_div_sd
+; SSE2: divsd %xmm1, %xmm0
+; AVX: vdivsd %xmm1, %xmm0, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <4 x float> @test2_add_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %a, i32 0
+ %2 = extractelement <4 x float> %b, i32 0
+ %add = fadd float %1, %2
+ %3 = insertelement <4 x float> %b, float %add, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test2_add_ss
+; SSE2: addss %xmm0, %xmm1
+; AVX: vaddss %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test2_sub_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %a, i32 0
+ %2 = extractelement <4 x float> %b, i32 0
+ %sub = fsub float %2, %1
+ %3 = insertelement <4 x float> %b, float %sub, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test2_sub_ss
+; SSE2: subss %xmm0, %xmm1
+; AVX: vsubss %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test2_mul_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %a, i32 0
+ %2 = extractelement <4 x float> %b, i32 0
+ %mul = fmul float %1, %2
+ %3 = insertelement <4 x float> %b, float %mul, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test2_mul_ss
+; SSE2: mulss %xmm0, %xmm1
+; AVX: vmulss %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test2_div_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %a, i32 0
+ %2 = extractelement <4 x float> %b, i32 0
+ %div = fdiv float %2, %1
+ %3 = insertelement <4 x float> %b, float %div, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test2_div_ss
+; SSE2: divss %xmm0, %xmm1
+; AVX: vdivss %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <2 x double> @test2_add_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %a, i32 0
+ %2 = extractelement <2 x double> %b, i32 0
+ %add = fadd double %1, %2
+ %3 = insertelement <2 x double> %b, double %add, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test2_add_sd
+; SSE2: addsd %xmm0, %xmm1
+; AVX: vaddsd %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <2 x double> @test2_sub_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %a, i32 0
+ %2 = extractelement <2 x double> %b, i32 0
+ %sub = fsub double %2, %1
+ %3 = insertelement <2 x double> %b, double %sub, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test2_sub_sd
+; SSE2: subsd %xmm0, %xmm1
+; AVX: vsubsd %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <2 x double> @test2_mul_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %a, i32 0
+ %2 = extractelement <2 x double> %b, i32 0
+ %mul = fmul double %1, %2
+ %3 = insertelement <2 x double> %b, double %mul, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test2_mul_sd
+; SSE2: mulsd %xmm0, %xmm1
+; AVX: vmulsd %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <2 x double> @test2_div_sd(<2 x double> %a, <2 x double> %b) {
+ %1 = extractelement <2 x double> %a, i32 0
+ %2 = extractelement <2 x double> %b, i32 0
+ %div = fdiv double %2, %1
+ %3 = insertelement <2 x double> %b, double %div, i32 0
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test2_div_sd
+; SSE2: divsd %xmm0, %xmm1
+; AVX: vdivsd %xmm0, %xmm1, %xmm0
+; CHECK-NOT: movsd
+; CHECK: ret
+
+
+define <4 x float> @test_multiple_add_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %add = fadd float %2, %1
+ %add2 = fadd float %2, %add
+ %3 = insertelement <4 x float> %a, float %add2, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_multiple_add_ss
+; CHECK: addss
+; CHECK: addss
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test_multiple_sub_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %sub = fsub float %2, %1
+ %sub2 = fsub float %2, %sub
+ %3 = insertelement <4 x float> %a, float %sub2, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_multiple_sub_ss
+; CHECK: subss
+; CHECK: subss
+; CHECK-NOT: movss
+; CHECK: ret
+
+
+define <4 x float> @test_multiple_mul_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %mul = fmul float %2, %1
+ %mul2 = fmul float %2, %mul
+ %3 = insertelement <4 x float> %a, float %mul2, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_multiple_mul_ss
+; CHECK: mulss
+; CHECK: mulss
+; CHECK-NOT: movss
+; CHECK: ret
+
+define <4 x float> @test_multiple_div_ss(<4 x float> %a, <4 x float> %b) {
+ %1 = extractelement <4 x float> %b, i32 0
+ %2 = extractelement <4 x float> %a, i32 0
+ %div = fdiv float %2, %1
+ %div2 = fdiv float %2, %div
+ %3 = insertelement <4 x float> %a, float %div2, i32 0
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_multiple_div_ss
+; CHECK: divss
+; CHECK: divss
+; CHECK-NOT: movss
+; CHECK: ret
+
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