[llvm] r196806 - Fix pattern match for movi with 0D result
Ana Pazos
apazos at codeaurora.org
Mon Dec 9 11:29:15 PST 2013
Author: apazos
Date: Mon Dec 9 13:29:14 2013
New Revision: 196806
URL: http://llvm.org/viewvc/llvm-project?rev=196806&view=rev
Log:
Fix pattern match for movi with 0D result
Patch by Jiangning Liu.
With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
llvm/trunk/test/CodeGen/AArch64/neon-aba-abd.ll
llvm/trunk/test/CodeGen/AArch64/neon-mov.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td?rev=196806&r1=196805&r2=196806&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td Mon Dec 9 13:29:14 2013
@@ -1437,9 +1437,8 @@ let isReMaterializable = 1 in {
def MOVIdi : NeonI_1VModImm<0b0, 0b1,
(outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
"movi\t $Rd, $Imm",
- [(set (f64 FPR64:$Rd),
- (f64 (bitconvert
- (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
+ [(set (v1i64 FPR64:$Rd),
+ (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
NoItinerary> {
let cmode = 0b1110;
}
Modified: llvm/trunk/test/CodeGen/AArch64/neon-aba-abd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-aba-abd.ll?rev=196806&r1=196805&r2=196806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-aba-abd.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-aba-abd.ll Mon Dec 9 13:29:14 2013
@@ -157,6 +157,16 @@ define <2 x i32> @test_sabd_v2i32(<2 x i
ret <2 x i32> %abd
}
+define <2 x i32> @test_sabd_v2i32_const() {
+; CHECK: test_sabd_v2i32_const:
+; CHECK: movi d1, #0xffffffff0000
+; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
+ %1 = tail call <2 x i32> @llvm.arm.neon.vabds.v2i32(
+ <2 x i32> <i32 -2147483648, i32 2147450880>,
+ <2 x i32> <i32 -65536, i32 65535>)
+ ret <2 x i32> %1
+}
+
define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; CHECK: test_saba_v2i32:
%abd = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
Modified: llvm/trunk/test/CodeGen/AArch64/neon-mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-mov.ll?rev=196806&r1=196805&r2=196806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-mov.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-mov.ll Mon Dec 9 13:29:14 2013
@@ -202,4 +202,16 @@ define <2 x double> @fmov2d() {
ret <2 x double> < double -1.2e1, double -1.2e1>
}
+define <2 x i32> @movi1d_1() {
+; CHECK: movi d0, #0xffffffff0000
+ ret <2 x i32> < i32 -65536, i32 65535>
+}
+
+
+declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
+define <2 x i32> @movi1d() {
+; CHECK: movi d1, #0xffffffff0000
+ %1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
+ ret <2 x i32> %1
+}
More information about the llvm-commits
mailing list