[llvm] r196735 - [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.

[Roman Divacky]

Hi Bill,

Can this be merged to 3.4?

On Sun, Dec 08, 2013 at 10:06:07PM -0000, Venkatraman Govindaraju wrote:
> Author: venkatra
> Date: Sun Dec  8 16:06:07 2013
> New Revision: 196735
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=196735&view=rev
> Log:
> [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.
>   This fixes PR18150.
> 
> Modified:
>     llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>     llvm/trunk/test/CodeGen/SPARC/rem.ll
> 
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=196735&r1=196734&r2=196735&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Sun Dec  8 16:06:07 2013
> @@ -1462,6 +1462,13 @@ SparcTargetLowering::SparcTargetLowering
>    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
>    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
>  
> +  if (Subtarget->is64Bit()) {
> +    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
> +    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
> +    setOperationAction(ISD::MULHU,     MVT::i64, Expand);
> +    setOperationAction(ISD::MULHS,     MVT::i64, Expand);
> +  }
> +
>    // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
>    setOperationAction(ISD::VASTART           , MVT::Other, Custom);
>    // VAARG needs to be lowered to not do unaligned accesses for doubles.
> 
> Modified: llvm/trunk/test/CodeGen/SPARC/rem.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/rem.ll?rev=196735&r1=196734&r2=196735&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/SPARC/rem.ll (original)
> +++ llvm/trunk/test/CodeGen/SPARC/rem.ll Sun Dec  8 16:06:07 2013
> @@ -21,3 +21,19 @@ define i64 @test2(i64 %X, i64 %Y) {
>          %tmp1 = urem i64 %X, %Y
>          ret i64 %tmp1
>  }
> +
> +; PR18150
> +; CHECK-LABEL: test3
> +; CHECK:       sethi 2545, [[R0:%[gilo][0-7]]]
> +; CHECK:       or    [[R0]], 379, [[R1:%[gilo][0-7]]]
> +; CHECK:       mulx  %o0, [[R1]], [[R2:%[gilo][0-7]]]
> +; CHECK:       udivx [[R2]], 1021, [[R3:%[gilo][0-7]]]
> +; CHECK:       mulx  [[R3]], 1021, [[R4:%[gilo][0-7]]]
> +; CHECK:       sub   [[R2]], [[R4]], %o0
> +
> +define i64 @test3(i64 %b) {
> +entry:
> +  %mul = mul i64 %b, 2606459
> +  %rem = urem i64 %mul, 1021
> +  ret i64 %rem
> +}
> 
> 
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