[llvm] r195788 - [AArch64] Add support for NEON scalar floating-point to integer convert
Bill Wendling
isanbard at gmail.com
Sat Nov 30 19:09:06 PST 2013
Done.!
-bw
On Nov 26, 2013, at 2:47 PM, Chad Rosier <mcrosier at codeaurora.org> wrote:
> Hi Tim/Bill,
> Would it be possible to pull this commit and the associated clang-side
> commit r195789 into the 3.4 branch?
>
> Thanks,
> Chad
>
>> Author: mcrosier
>> Date: Tue Nov 26 16:17:37 2013
>> New Revision: 195788
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=195788&view=rev
>> Log:
>> [AArch64] Add support for NEON scalar floating-point to integer convert
>> instructions.
>>
>> Added:
>> llvm/trunk/test/CodeGen/AArch64/neon-scalar-fcvt.ll
>> Modified:
>> llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td
>> llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
>> llvm/trunk/test/MC/AArch64/neon-diagnostics.s
>> llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s
>> llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
>>
>> Modified: llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td?rev=195788&r1=195787&r2=195788&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td (original)
>> +++ llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td Tue Nov 26 16:17:37
>> 2013
>> @@ -54,6 +54,10 @@ def int_aarch64_neon_fcvtas :
>> Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
>> def int_aarch64_neon_fcvtau :
>> Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
>> +def int_aarch64_neon_fcvtzs :
>> + Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
>> +def int_aarch64_neon_fcvtzu :
>> + Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
>>
>> // Vector maxNum (Floating Point)
>> def int_aarch64_neon_vmaxnm : Neon_2Arg_Intrinsic;
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td?rev=195788&r1=195787&r2=195788&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td Tue Nov 26 16:17:37
>> 2013
>> @@ -4245,7 +4245,7 @@ multiclass NeonI_Scalar2SameMisc_SD_size
>> }
>>
>> multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string
>> asmop> {
>> - def dd: NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64,
>> FPR64>;
>> + def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64,
>> FPR64>;
>> }
>>
>> multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string
>> asmop>
>> @@ -4255,6 +4255,9 @@ multiclass NeonI_Scalar2SameMisc_BHSD_si
>> def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32,
>> FPR32>;
>> }
>>
>> +class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string
>> asmop>
>> + : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
>> +
>> multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
>> string asmop> {
>> def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8,
>> FPR16>;
>> @@ -4281,6 +4284,20 @@ multiclass NeonI_Scalar2SameMisc_accum_B
>> }
>> }
>>
>> +class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator
>> opnode,
>> + Instruction INSTD>
>> + : Pat<(v1f32 (opnode (v1f64 FPR64:$Rn))),
>> + (INSTD FPR64:$Rn)>;
>> +
>> +multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator
>> opnode,
>> + Instruction INSTS,
>> + Instruction INSTD>
>> {
>> + def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn))),
>> + (INSTS FPR32:$Rn)>;
>> + def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
>> + (INSTD FPR64:$Rn)>;
>> +}
>> +
>> multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator
>> Sopnode,
>> SDPatternOperator
>> Dopnode,
>> Instruction INSTS,
>> @@ -4885,6 +4902,51 @@ defm : Neon_Scalar2SameMisc_cvt_SD_size_
>> int_aarch64_neon_vcvtf64_u64,
>> UCVTFss, UCVTFdd>;
>>
>> +// Scalar Floating-point Converts
>> +def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
>> +def :
>> Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
>> + FCVTXN>;
>> +
>> +defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
>> + FCVTNSss, FCVTNSdd>;
>> +
>> +defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
>> + FCVTNUss, FCVTNUdd>;
>> +
>> +defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
>> + FCVTMSss, FCVTMSdd>;
>> +
>> +defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
>> + FCVTMUss, FCVTMUdd>;
>> +
>> +defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
>> + FCVTASss, FCVTASdd>;
>> +
>> +defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
>> + FCVTAUss, FCVTAUdd>;
>> +
>> +defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
>> + FCVTPSss, FCVTPSdd>;
>> +
>> +defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
>> + FCVTPUss, FCVTPUdd>;
>> +
>> +defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
>> + FCVTZSss, FCVTZSdd>;
>> +
>> +defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
>> +defm :
>> Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
>> + FCVTZUss, FCVTZUdd>;
>> +
>> // Scalar Floating-point Reciprocal Estimate
>> defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
>> defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
>>
>> Added: llvm/trunk/test/CodeGen/AArch64/neon-scalar-fcvt.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-scalar-fcvt.ll?rev=195788&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/neon-scalar-fcvt.ll (added)
>> +++ llvm/trunk/test/CodeGen/AArch64/neon-scalar-fcvt.ll Tue Nov 26
>> 16:17:37 2013
>> @@ -0,0 +1,255 @@
>> +; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck
>> %s
>> +
>> +;; Scalar Floating-point Convert
>> +
>> +define float @test_vcvtxn(double %a) {
>> +; CHECK: test_vcvtxn
>> +; CHECK: fcvtxn {{s[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtf.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtf1.i = tail call <1 x float>
>> @llvm.aarch64.neon.fcvtxn.v1f32.v1f64(<1 x double> %vcvtf.i)
>> + %0 = extractelement <1 x float> %vcvtf1.i, i32 0
>> + ret float %0
>> +}
>> +
>> +declare <1 x float> @llvm.aarch64.neon.fcvtxn.v1f32.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtass(float %a) {
>> +; CHECK: test_vcvtass
>> +; CHECK: fcvtas {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtas.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtas1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtas.v1i32.v1f32(<1 x float> %vcvtas.i)
>> + %0 = extractelement <1 x i32> %vcvtas1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_test_vcvtasd(double %a) {
>> +; CHECK: test_test_vcvtasd
>> +; CHECK: fcvtas {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtas.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtas1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %vcvtas.i)
>> + %0 = extractelement <1 x i64> %vcvtas1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtaus(float %a) {
>> +; CHECK: test_vcvtaus
>> +; CHECK: fcvtau {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtau.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtau1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtau.v1i32.v1f32(<1 x float> %vcvtau.i)
>> + %0 = extractelement <1 x i32> %vcvtau1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtaud(double %a) {
>> +; CHECK: test_vcvtaud
>> +; CHECK: fcvtau {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtau.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtau1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %vcvtau.i)
>> + %0 = extractelement <1 x i64> %vcvtau1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtmss(float %a) {
>> +; CHECK: test_vcvtmss
>> +; CHECK: fcvtms {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtms.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtms1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtms.v1i32.v1f32(<1 x float> %vcvtms.i)
>> + %0 = extractelement <1 x i32> %vcvtms1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtmd_s64_f64(double %a) {
>> +; CHECK: test_vcvtmd_s64_f64
>> +; CHECK: fcvtms {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtms.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtms1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %vcvtms.i)
>> + %0 = extractelement <1 x i64> %vcvtms1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtmus(float %a) {
>> +; CHECK: test_vcvtmus
>> +; CHECK: fcvtmu {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtmu.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtmu1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtmu.v1i32.v1f32(<1 x float> %vcvtmu.i)
>> + %0 = extractelement <1 x i32> %vcvtmu1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtmud(double %a) {
>> +; CHECK: test_vcvtmud
>> +; CHECK: fcvtmu {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtmu.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtmu1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %vcvtmu.i)
>> + %0 = extractelement <1 x i64> %vcvtmu1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtnss(float %a) {
>> +; CHECK: test_vcvtnss
>> +; CHECK: fcvtns {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtns.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtns1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtns.v1i32.v1f32(<1 x float> %vcvtns.i)
>> + %0 = extractelement <1 x i32> %vcvtns1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtnd_s64_f64(double %a) {
>> +; CHECK: test_vcvtnd_s64_f64
>> +; CHECK: fcvtns {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtns.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtns1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> %vcvtns.i)
>> + %0 = extractelement <1 x i64> %vcvtns1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtnus(float %a) {
>> +; CHECK: test_vcvtnus
>> +; CHECK: fcvtnu {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtnu.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtnu1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtnu.v1i32.v1f32(<1 x float> %vcvtnu.i)
>> + %0 = extractelement <1 x i32> %vcvtnu1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtnud(double %a) {
>> +; CHECK: test_vcvtnud
>> +; CHECK: fcvtnu {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtnu.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtnu1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %vcvtnu.i)
>> + %0 = extractelement <1 x i64> %vcvtnu1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtpss(float %a) {
>> +; CHECK: test_vcvtpss
>> +; CHECK: fcvtps {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtps.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtps1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtps.v1i32.v1f32(<1 x float> %vcvtps.i)
>> + %0 = extractelement <1 x i32> %vcvtps1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtpd_s64_f64(double %a) {
>> +; CHECK: test_vcvtpd_s64_f64
>> +; CHECK: fcvtps {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtps.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtps1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %vcvtps.i)
>> + %0 = extractelement <1 x i64> %vcvtps1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtpus(float %a) {
>> +; CHECK: test_vcvtpus
>> +; CHECK: fcvtpu {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtpu.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtpu1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtpu.v1i32.v1f32(<1 x float> %vcvtpu.i)
>> + %0 = extractelement <1 x i32> %vcvtpu1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtpud(double %a) {
>> +; CHECK: test_vcvtpud
>> +; CHECK: fcvtpu {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtpu.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtpu1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> %vcvtpu.i)
>> + %0 = extractelement <1 x i64> %vcvtpu1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtss(float %a) {
>> +; CHECK: test_vcvtss
>> +; CHECK: fcvtzs {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtzs.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtzs1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtzs.v1i32.v1f32(<1 x float> %vcvtzs.i)
>> + %0 = extractelement <1 x i32> %vcvtzs1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtd_s64_f64(double %a) {
>> +; CHECK: test_vcvtd_s64_f64
>> +; CHECK: fcvtzs {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvzs.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvzs1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %vcvzs.i)
>> + %0 = extractelement <1 x i64> %vcvzs1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double>)
>> +
>> +define i32 @test_vcvtus(float %a) {
>> +; CHECK: test_vcvtus
>> +; CHECK: fcvtzu {{s[0-9]}}, {{s[0-9]}}
>> +entry:
>> + %vcvtzu.i = insertelement <1 x float> undef, float %a, i32 0
>> + %vcvtzu1.i = tail call <1 x i32>
>> @llvm.aarch64.neon.fcvtzu.v1i32.v1f32(<1 x float> %vcvtzu.i)
>> + %0 = extractelement <1 x i32> %vcvtzu1.i, i32 0
>> + ret i32 %0
>> +}
>> +
>> +declare <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.v1f32(<1 x float>)
>> +
>> +define i64 @test_vcvtud(double %a) {
>> +; CHECK: test_vcvtud
>> +; CHECK: fcvtzu {{d[0-9]}}, {{d[0-9]}}
>> +entry:
>> + %vcvtzu.i = insertelement <1 x double> undef, double %a, i32 0
>> + %vcvtzu1.i = tail call <1 x i64>
>> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %vcvtzu.i)
>> + %0 = extractelement <1 x i64> %vcvtzu1.i, i32 0
>> + ret i64 %0
>> +}
>> +
>> +declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double>)
>>
>> Modified: llvm/trunk/test/MC/AArch64/neon-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=195788&r1=195787&r2=195788&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/neon-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/neon-diagnostics.s Tue Nov 26 16:17:37 2013
>> @@ -7141,3 +7141,163 @@
>> // CHECK-ERROR: error: invalid number of vectors
>> // CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b,
>> v5.16b}, v2.8b
>> // CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To
>> +// Odd
>> +//----------------------------------------------------------------------
>> +
>> + fcvtxn s0, s1
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtxn s0, s1
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
>> +// With Ties To Away
>> +//----------------------------------------------------------------------
>> +
>> + fcvtas s0, d0
>> + fcvtas d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtas s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtas d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding To
>> +// Nearest With Ties To Away
>> +//----------------------------------------------------------------------
>> +
>> + fcvtau s0, d0
>> + fcvtau d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtau s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtau d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding Toward
>> +// Minus Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtms s0, d0
>> + fcvtms d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtms s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtms d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +// Minus Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtmu s0, d0
>> + fcvtmu d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtmu s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtmu d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
>> +// With Ties To Even
>> +//----------------------------------------------------------------------
>> +
>> + fcvtns s0, d0
>> + fcvtns d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtns s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtns d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding To
>> +// Nearest With Ties To Even
>> +//----------------------------------------------------------------------
>> +
>> + fcvtnu s0, d0
>> + fcvtnu d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtnu s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtnu d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding Toward
>> +// Positive Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtps s0, d0
>> + fcvtps d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtps s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtps d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +// Positive Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtpu s0, d0
>> + fcvtpu d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtpu s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtpu d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero
>> +//----------------------------------------------------------------------
>> +
>> + fcvtzs s0, d0
>> + fcvtzs d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtzs s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtzs d0, s0
>> +// CHECK-ERROR: ^
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +// Zero
>> +//----------------------------------------------------------------------
>> +
>> + fcvtzu s0, d0
>> + fcvtzu d0, s0
>> +
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtzu s0, d0
>> +// CHECK-ERROR: ^
>> +// CHECK-ERROR: error: invalid operand for instruction
>> +// CHECK-ERROR: fcvtzu d0, s0
>> +// CHECK-ERROR: ^
>>
>> Modified: llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s?rev=195788&r1=195787&r2=195788&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s (original)
>> +++ llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s Tue Nov 26 16:17:37 2013
>> @@ -61,3 +61,121 @@
>>
>> // CHECK: fcvtzu s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x7f]
>> // CHECK: fcvtzu d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x7f]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To
>> +// Odd
>> +//----------------------------------------------------------------------
>> +
>> + fcvtxn s22, d13
>> +
>> +// CHECK: fcvtxn s22, d13 // encoding: [0xb6,0x69,0x61,0x7e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
>> +// With Ties To Away
>> +//----------------------------------------------------------------------
>> +
>> + fcvtas s12, s13
>> + fcvtas d21, d14
>> +
>> +// CHECK: fcvtas s12, s13 // encoding: [0xac,0xc9,0x21,0x5e]
>> +// CHECK: fcvtas d21, d14 // encoding: [0xd5,0xc9,0x61,0x5e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding To
>> +// Nearest With Ties To Away
>> +//----------------------------------------------------------------------
>> +
>> + fcvtau s12, s13
>> + fcvtau d21, d14
>> +
>> +// CHECK: fcvtau s12, s13 // encoding: [0xac,0xc9,0x21,0x7e]
>> +// CHECK: fcvtau d21, d14 // encoding: [0xd5,0xc9,0x61,0x7e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding Toward
>> +// Minus Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtms s22, s13
>> + fcvtms d21, d14
>> +
>> +// CHECK: fcvtms s22, s13 // encoding: [0xb6,0xb9,0x21,0x5e]
>> +// CHECK: fcvtms d21, d14 // encoding: [0xd5,0xb9,0x61,0x5e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +// Minus Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtmu s12, s13
>> + fcvtmu d21, d14
>> +
>> +// CHECK: fcvtmu s12, s13 // encoding: [0xac,0xb9,0x21,0x7e]
>> +// CHECK: fcvtmu d21, d14 // encoding: [0xd5,0xb9,0x61,0x7e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
>> +// With Ties To Even
>> +//----------------------------------------------------------------------
>> +
>> + fcvtns s22, s13
>> + fcvtns d21, d14
>> +
>> +// CHECK: fcvtns s22, s13 // encoding: [0xb6,0xa9,0x21,0x5e]
>> +// CHECK: fcvtns d21, d14 // encoding: [0xd5,0xa9,0x61,0x5e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding To
>> +// Nearest With Ties To Even
>> +//----------------------------------------------------------------------
>> +
>> + fcvtnu s12, s13
>> + fcvtnu d21, d14
>> +
>> +// CHECK: fcvtnu s12, s13 // encoding: [0xac,0xa9,0x21,0x7e]
>> +// CHECK: fcvtnu d21, d14 // encoding: [0xd5,0xa9,0x61,0x7e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding Toward
>> +// Positive Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtps s22, s13
>> + fcvtps d21, d14
>> +
>> +// CHECK: fcvtps s22, s13 // encoding: [0xb6,0xa9,0xa1,0x5e]
>> +// CHECK: fcvtps d21, d14 // encoding: [0xd5,0xa9,0xe1,0x5e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +// Positive Infinity
>> +//----------------------------------------------------------------------
>> +
>> + fcvtpu s12, s13
>> + fcvtpu d21, d14
>> +
>> +// CHECK: fcvtpu s12, s13 // encoding: [0xac,0xa9,0xa1,0x7e]
>> +// CHECK: fcvtpu d21, d14 // encoding: [0xd5,0xa9,0xe1,0x7e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero
>> +//----------------------------------------------------------------------
>> +
>> + fcvtzs s12, s13
>> + fcvtzs d21, d14
>> +
>> +// CHECK: fcvtzs s12, s13 // encoding: [0xac,0xb9,0xa1,0x5e]
>> +// CHECK: fcvtzs d21, d14 // encoding: [0xd5,0xb9,0xe1,0x5e]
>> +
>> +//----------------------------------------------------------------------
>> +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +// Zero
>> +//----------------------------------------------------------------------
>> +
>> + fcvtzu s12, s13
>> + fcvtzu d21, d14
>> +
>> +// CHECK: fcvtzu s12, s13 // encoding: [0xac,0xb9,0xa1,0x7e]
>> +// CHECK: fcvtzu d21, d14 // encoding: [0xd5,0xb9,0xe1,0x7e]
>>
>> Modified: llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt?rev=195788&r1=195787&r2=195788&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
>> (original)
>> +++ llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt Tue Nov
>> 26 16:17:37 2013
>> @@ -2510,3 +2510,102 @@
>> # CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
>> # CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b
>>
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Lower Precision Narrow, Rounding To
>> +# Odd
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtxn s22, d13
>> +0xb6,0x69,0x61,0x7e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
>> +# With Ties To Away
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtas s12, s13
>> +# CHECK: fcvtas d21, d14
>> +
>> +0xac,0xc9,0x21,0x5e
>> +0xd5,0xc9,0x61,0x5e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Unsigned Integer, Rounding To
>> +# Nearest With Ties To Away
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtau s12, s13
>> +# CHECK: fcvtau d21, d14
>> +0xac,0xc9,0x21,0x7e
>> +0xd5,0xc9,0x61,0x7e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Signed Integer, Rounding Toward
>> +# Minus Infinity
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtms s22, s13
>> +# CHECK: fcvtms d21, d14
>> +0xb6,0xb9,0x21,0x5e
>> +0xd5,0xb9,0x61,0x5e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +# Minus Infinity
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtmu s12, s13
>> +# CHECK: fcvtmu d21, d14
>> +0xac,0xb9,0x21,0x7e
>> +0xd5,0xb9,0x61,0x7e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
>> +# With Ties To Even
>> +#----------------------------------------------------------------------
>> +
>> +# CHECK: fcvtns s22, s13
>> +# CHECK: fcvtns d21, d14
>> +
>> +0xb6,0xa9,0x21,0x5e
>> +0xd5,0xa9,0x61,0x5e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Unsigned Integer, Rounding To
>> +# Nearest With Ties To Even
>> +#----------------------------------------------------------------------
>> +
>> +# CHECK: fcvtnu s12, s13
>> +# CHECK: fcvtnu d21, d14
>> +0xac,0xa9,0x21,0x7e
>> +0xd5,0xa9,0x61,0x7e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Signed Integer, Rounding Toward
>> +# Positive Infinity
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtps s22, s13
>> +# CHECK: fcvtps d21, d14
>> +0xb6,0xa9,0xa1,0x5e
>> +0xd5,0xa9,0xe1,0x5e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +# Positive Infinity
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtpu s12, s13
>> +# CHECK: fcvtpu d21, d14
>> +0xac,0xa9,0xa1,0x7e
>> +0xd5,0xa9,0xe1,0x7e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtzs s12, s13
>> +# CHECK: fcvtzs d21, d14
>> +0xac,0xb9,0xa1,0x5e
>> +0xd5,0xb9,0xe1,0x5e
>> +
>> +#----------------------------------------------------------------------
>> +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward
>> +# Zero
>> +#----------------------------------------------------------------------
>> +# CHECK: fcvtzu s12, s13
>> +# CHECK: fcvtzu d21, d14
>> +0xac,0xb9,0xa1,0x7e
>> +0xd5,0xb9,0xe1,0x7e
>>
>>
>> _______________________________________________
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