[llvm] r195948 - Fixup PPC440 load/store operand latencies
Hal Finkel
hfinkel at anl.gov
Thu Nov 28 22:19:44 PST 2013
Author: hfinkel
Date: Fri Nov 29 00:19:43 2013
New Revision: 195948
URL: http://llvm.org/viewvc/llvm-project?rev=195948&view=rev
Log:
Fixup PPC440 load/store operand latencies
The operand latencies for loads and stores in the PPC440 itinerary were wrong
(the store operands are all inputs, and the "with update" (pre-increment)
instructions need a latency for the additional output).
Modified:
llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td?rev=195948&r1=195947&r2=195948&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td Fri Nov 29 00:19:43 2013
@@ -228,70 +228,70 @@ def PPC440Itineraries : ProcessorItinera
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
- [5, 1],
+ [5, 1, 1],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
- [5, 1],
+ [5, 2, 1, 1],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
- [4, 1],
+ [1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
- [4, 1],
+ [2, 1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1, 1],
+ [1, 1, 1],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1, 1],
+ [2, 1, 1, 1],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
@@ -305,28 +305,28 @@ def PPC440Itineraries : ProcessorItinera
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [5, 1, 1],
+ [5, 2, 1, 1],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
@@ -335,21 +335,21 @@ def PPC440Itineraries : ProcessorItinera
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<2, [P440_LWB]>],
- [4, 1],
+ [2, 1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
@@ -358,7 +358,7 @@ def PPC440Itineraries : ProcessorItinera
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
@@ -367,7 +367,7 @@ def PPC440Itineraries : ProcessorItinera
InstrStage<1, [P440_AGEN]>,
InstrStage<1, [P440_CRD]>,
InstrStage<1, [P440_LWB]>],
- [4, 1],
+ [4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
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