[llvm] r195932 - Silence sign-compare warning and reduce nesting.

[Benjamin Kramer]

Author: d0k
Date: Thu Nov 28 13:58:56 2013
New Revision: 195932

URL: http://llvm.org/viewvc/llvm-project?rev=195932&view=rev
Log:
Silence sign-compare warning and reduce nesting.

No functionality change.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=195932&r1=195931&r2=195932&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Nov 28 13:58:56 2013
@@ -4239,13 +4239,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFF
                          DAG.getConstant(Lane + ExtLane, MVT::i64));
     }
     // Test if V1 is a CONCAT_VECTORS.
-    if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
-      if (V1.getOperand(1).getOpcode() == ISD::UNDEF) {
-        assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements())
-               && "Invalid vector lane access");
-        return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
-                           DAG.getConstant(Lane, MVT::i64));
-      }
+    if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
+        V1.getOperand(1).getOpcode() == ISD::UNDEF) {
+      SDValue Op0 = V1.getOperand(0);
+      assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
+             "Invalid vector lane access");
+      return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
+                         DAG.getConstant(Lane, MVT::i64));
     }
 
     return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,