[PATCH] [PATCH][AArch64]Fix a bug about disassembling post-index load single element to 4 vectors

[Hao Liu]

Hi t.p.northover,

Hi Tim and reviewers,

This patch fixes a minor bug when decoding the ld4 instruction. Due to my carelessness, the transfered bytes decoded is the same as ld3 (i.e. 3, 6, 12, 24). As we know, one vector for different lane layouts (B, H, S, D) should be transfered 1, 2, 4, 8 bytes. So for 4 vectors, the transfered bytes should be 4, 8, 16, 32. This is caused by copy and past. ST4 and other instructions are correct, which have been double checked.

Review please.

Thanks,
-Hao

http://llvm-reviews.chandlerc.com/D2279

Files:
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  test/MC/Disassembler/AArch64/neon-instructions.txt

Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
===================================================================
--- lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1342,13 +1342,13 @@
   case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
     switch (Opc) {
     case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
-      TransferBytes = 3; break;
+      TransferBytes = 4; break;
     case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
-      TransferBytes = 6; break;
+      TransferBytes = 8; break;
     case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
-      TransferBytes = 12; break;
+      TransferBytes = 16; break;
     case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
-      TransferBytes = 24; break;
+      TransferBytes = 32; break;
     }
     IsLoad = true;
     NumVecs = 4;
Index: test/MC/Disassembler/AArch64/neon-instructions.txt
===================================================================
--- test/MC/Disassembler/AArch64/neon-instructions.txt
+++ test/MC/Disassembler/AArch64/neon-instructions.txt
@@ -2129,7 +2129,8 @@
 # CHECK: ld1 {v0.b}[9], [x0], #1
 # CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
 # CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
-# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24
+# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
+# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0
 # CHECK: st1 {v0.d}[1], [x0], #8
 # CHECK: st2 {v31.s, v0.s}[3], [sp], #8
 # CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6
@@ -2138,6 +2139,7 @@
 0xef,0x59,0xff,0x4d
 0xff,0xb3,0xc3,0x4d
 0x00,0xa4,0xff,0x4d
+0x00,0x78,0xe0,0x4d
 0x00,0x84,0x9f,0x4d
 0xff,0x93,0xbf,0x4d
 0xef,0x79,0x9f,0x4d
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