[PATCH] [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.

[Kevin Qin]

http://llvm-reviews.chandlerc.com/D2278

Files:
  lib/Target/AArch64/AArch64InstrNEON.td
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Index: lib/Target/AArch64/AArch64InstrNEON.td
===================================================================
--- lib/Target/AArch64/AArch64InstrNEON.td
+++ lib/Target/AArch64/AArch64InstrNEON.td
@@ -7850,41 +7850,43 @@
 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
 
 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
-  def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
-                          (outs VPR128:$Rd),
-                          (ins VPR64:$Rn, uimm_exact8:$Imm),
-                          asmop # "\t$Rd.8h, $Rn.8b, $Imm",
-                          [], NoItinerary>;
-
-  def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
-                          (outs VPR128:$Rd),
-                          (ins VPR64:$Rn, uimm_exact16:$Imm),
-                          asmop # "\t$Rd.4s, $Rn.4h, $Imm",
-                          [], NoItinerary>;
-
-  def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
-                          (outs VPR128:$Rd),
-                          (ins VPR64:$Rn, uimm_exact32:$Imm),
-                          asmop # "\t$Rd.2d, $Rn.2s, $Imm",
-                          [], NoItinerary>;
-
-  def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
-                          (outs VPR128:$Rd),
-                          (ins VPR128:$Rn, uimm_exact8:$Imm),
-                          asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
-                          [], NoItinerary>;
-
-  def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
-                          (outs VPR128:$Rd),
-                          (ins VPR128:$Rn, uimm_exact16:$Imm),
-                          asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
-                          [], NoItinerary>;
-
-  def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
-                          (outs VPR128:$Rd),
-                          (ins VPR128:$Rn, uimm_exact32:$Imm),
-                          asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
-                          [], NoItinerary>;
+  let DecoderMethod = "DecodeSHLLInstruction" in {
+    def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
+                            (outs VPR128:$Rd),
+                            (ins VPR64:$Rn, uimm_exact8:$Imm),
+                            asmop # "\t$Rd.8h, $Rn.8b, $Imm",
+                            [], NoItinerary>;
+    
+    def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
+                            (outs VPR128:$Rd),
+                            (ins VPR64:$Rn, uimm_exact16:$Imm),
+                            asmop # "\t$Rd.4s, $Rn.4h, $Imm",
+                            [], NoItinerary>;
+    
+    def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
+                            (outs VPR128:$Rd),
+                            (ins VPR64:$Rn, uimm_exact32:$Imm),
+                            asmop # "\t$Rd.2d, $Rn.2s, $Imm",
+                            [], NoItinerary>;
+    
+    def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
+                            (outs VPR128:$Rd),
+                            (ins VPR128:$Rn, uimm_exact8:$Imm),
+                            asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
+                            [], NoItinerary>;
+    
+    def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
+                            (outs VPR128:$Rd),
+                            (ins VPR128:$Rn, uimm_exact16:$Imm),
+                            asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
+                            [], NoItinerary>;
+    
+    def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
+                            (outs VPR128:$Rd),
+                            (ins VPR128:$Rn, uimm_exact32:$Imm),
+                            asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
+                            [], NoItinerary>;
+  }
 }
 
 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
===================================================================
--- lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -238,6 +238,10 @@
                                                    uint64_t Address,
                                                    const void *Decoder);
 
+static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
+                                          uint64_t Address,
+                                          const void *Decoder);
+
 static bool Check(DecodeStatus &Out, DecodeStatus In);
 
 #include "AArch64GenDisassemblerTables.inc"
@@ -1534,3 +1538,35 @@
 
   return MCDisassembler::Success;
 }
+
+static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+  unsigned size = fieldFromInstruction(Insn, 22, 2);
+  unsigned Q = fieldFromInstruction(Insn, 30, 1);
+
+  DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
+
+  if(Q)
+    DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
+  else
+    DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
+
+  switch (size) {
+  case 0:
+    Inst.addOperand(MCOperand::CreateImm(8));
+    break;
+  case 1:
+    Inst.addOperand(MCOperand::CreateImm(16));
+    break;
+  case 2:
+    Inst.addOperand(MCOperand::CreateImm(32));
+    break;
+  default :
+    return MCDisassembler::Fail;
+  }
+  return MCDisassembler::Success;
+}
+
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