[PATCH] Refactored the implementation of AArch64 NEON instruction ZIP, UZP and TRN and fix a bug when mixed use of vget_high_u8() and vuzp_u8().

[Kevin Qin]

  made some small changes as comments and commited as r195716.


  2013/11/25 Tim Northover <t.p.northover at gmail.com>

  >
  >   Hi Kevin,
  >
  >   This looks like a good change too. Just a couple of minor nits.
  >
  >   Cheers.
  >
  >   Tim.
  >
  >
  > ================
  > Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:3843
  > @@ +3842,3 @@
  > +bool
  > +AArch64TargetLowering::isShuffleVector(SDValue Op, SelectionDAG &DAG,
  > SDValue &Res) const {
  > +  SDLoc DL(Op);
  > ----------------
  > Could this be called something like "isKnownShuffleVector"? It seems to be
  > checking more than just whether the input *is* a shuffle.
  >
  > ================
  > Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:3853
  > @@ +3852,3 @@
  > +  for (unsigned i = 0 ; i < NumElts; ++i) {
  > +    SDValue Ele = Op.getOperand(i);
  > +    if(Ele.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
  > ----------------
  > "Elt" would be more consistent, I think.
  >
  > ================
  > Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:3849
  > @@ +3848,3 @@
  > +  int Mask[16];
  > +  SDValue V0, V1;
  > +
  > ----------------
  > Can we assert that we've got a BUILD_VECTOR? As much for documentation as
  > anything else. I had to look up what it was being used on in the source
  > while reading this.
  >
  >
  > http://llvm-reviews.chandlerc.com/D2265
  >

http://llvm-reviews.chandlerc.com/D2265