[llvm] r195041 - R600/SI: Fix multiple SGPR reads when using VCC.

[Matt Arsenault]

Author: arsenm
Date: Mon Nov 18 14:09:50 2013
New Revision: 195041

URL: http://llvm.org/viewvc/llvm-project?rev=195041&view=rev
Log:
R600/SI: Fix multiple SGPR reads when using VCC.

No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
    llvm/trunk/test/CodeGen/R600/add_i64.ll

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=195041&r1=195040&r2=195041&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Mon Nov 18 14:09:50 2013
@@ -417,6 +417,7 @@ void SIInstrInfo::legalizeOpWithMove(Mac
   MachineOperand &MO = MI->getOperand(OpIdx);
   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
   unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
+  // XXX - This shouldn't be VSrc
   const TargetRegisterClass *RC = RI.getRegClass(RCID);
   unsigned Opcode = AMDGPU::V_MOV_B32_e32;
   if (MO.isReg()) {
@@ -442,8 +443,24 @@ void SIInstrInfo::legalizeOperands(Machi
 
   // Legalize VOP2
   if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
+    MachineOperand &Src0 = MI->getOperand(Src0Idx);
     MachineOperand &Src1 = MI->getOperand(Src1Idx);
 
+    // If the instruction implicitly reads VCC, we can't have any SGPR operands,
+    // so move any.
+    bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
+    if (ReadsVCC && Src0.isReg() &&
+        RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
+      legalizeOpWithMove(MI, Src0Idx);
+      return;
+    }
+
+    if (ReadsVCC && Src1.isReg() &&
+        RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
+      legalizeOpWithMove(MI, Src1Idx);
+      return;
+    }
+
     // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
     // be the first operand, and there can only be one.
     if (Src1.isImm() || Src1.isFPImm() ||
@@ -456,6 +473,7 @@ void SIInstrInfo::legalizeOperands(Machi
     }
   }
 
+  // XXX - Do any VOP3 instructions read VCC?
   // Legalize VOP3
   if (isVOP3(MI->getOpcode())) {
     int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};

Modified: llvm/trunk/test/CodeGen/R600/add_i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add_i64.ll?rev=195041&r1=195040&r2=195041&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/add_i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/add_i64.ll Mon Nov 18 14:09:50 2013
@@ -18,13 +18,28 @@ define void @test_i64_vreg(i64 addrspace
   ret void
 }
 
-; SI-LABEL: @test_i64_sreg:
-define void @test_i64_sreg(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) {
-  %result = add i64 %a, %b
+; SI-LABEL: @one_sgpr:
+define void @one_sgpr(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
+  %foo = load i64 addrspace(1)* %in, align 8
+  %result = add i64 %foo, %a
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
+; FIXME: This case is broken
+;
+; Swap the arguments. Check that the SGPR -> VGPR copy works with the
+; SGPR as other operand.
+;
+; XXXSI-LABEL: @one_sgpr_reversed:
+; define void @one_sgpr_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
+;   %foo = load i64 addrspace(1)* %in, align 8
+;   %result = add i64 %a, %foo
+;   store i64 %result, i64 addrspace(1)* %out
+;   ret void
+; }
+
+
 ; SI-LABEL: @test_v2i64_sreg:
 define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
   %result = add <2 x i64> %a, %b