[PATCH] Avoid generating SHLD/SHRD for architectures that are known to have poor latency for these instructions.

[Eric Christopher]

  Some trivial comments on the patch, otherwise it looks pretty good. I am curious about the IvyBridge and above that you mentioned, how'd you test?


================
Comment at: test/CodeGen/X86/x86-64-double-precision-shift-left.ll:2
@@ +1,3 @@
+; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
+; Verify that for the platforms with ... we generate expanded shifts.
+
----------------
Missed some of your comment here?

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Comment at: lib/Target/X86/X86Subtarget.cpp:275
@@ -266,1 +274,3 @@
+
+
     // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
----------------
Extra whitespace.

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Comment at: test/CodeGen/X86/x86-64-double-precision-shift-right.ll:2
@@ +1,3 @@
+; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
+; Verify that for the platforms with ... we generate expanded shifts.
+
----------------
Same here.

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Comment at: test/CodeGen/X86/x86-64-double-shifts-var.ll:1
@@ +1,2 @@
+; RUN: llc < %s -march=x86-64 -mcpu=athlon | not grep sh\[lr\]d
+; RUN: llc < %s -march=x86-64 -mcpu=athlon-tbird | not grep sh\[lr\]d
----------------
Should use FileCheck instead of grep.


http://llvm-reviews.chandlerc.com/D2177