[llvm] r194806 - [mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.
Daniel Sanders
daniel.sanders at imgtec.com
Fri Nov 15 03:04:17 PST 2013
Author: dsanders
Date: Fri Nov 15 05:04:16 2013
New Revision: 194806
URL: http://llvm.org/viewvc/llvm-project?rev=194806&view=rev
Log:
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.
Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConstant() produces illegal types. These have been temporarily
marked XFAIL and the XFAIL flag will be removed when
SelectionDAG::getConstant() is fixed.
There are three categories of failure:
* Immediate instructions are not selected in one endian mode.
* Immediates used in ldi.[bhwd] must be different according to endianness.
(this only affects cases where the 'wrong' ldi is used to load the correct
bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...)))
* Non-immediate instructions that rely on immediates affected by the
previous two categories as part of their match pattern.
For example, the bset match pattern is the vector equivalent of
'ws | (1 << wt)'.
One test needed correcting to expect different output depending on whether big
or little endian was in use. This test was
test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category
of failure shown above. The little endian version of this test is named
basic_operations_little.ll and will be merged back into basic_operations.ll in
a follow up commit now that FileCheck supports multiple check prefixes.
Reviewers: bkramer, jacksprat, dsanders
Reviewed By: dsanders
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1972
Added:
llvm/trunk/test/CodeGen/Mips/msa/basic_operations_little.ll
- copied, changed from r194796, llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll
llvm/trunk/test/CodeGen/Mips/msa/endian.ll
Modified:
llvm/trunk/test/CodeGen/Mips/msa/2r.ll
llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll
llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll
llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll
llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll
llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll
llvm/trunk/test/CodeGen/Mips/msa/bit.ll
llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll
llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
llvm/trunk/test/CodeGen/Mips/msa/compare.ll
llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
llvm/trunk/test/CodeGen/Mips/msa/i10.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll
llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll
llvm/trunk/test/CodeGen/Mips/msa/i8.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll
llvm/trunk/test/CodeGen/Mips/msa/spill.ll
llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll
Modified: llvm/trunk/test/CodeGen/Mips/msa/2r.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2r.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2r.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2r.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; convert scalars to vectors.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fill_b_ARG1 = global i32 23, align 16
@llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; are encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
@llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll Fri Nov 15 05:04:16 2013
@@ -3,6 +3,7 @@
; as fclass are also here.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'a'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
; It should fail to compile without fp64.
; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,8 @@
; There are lots of these so this covers those beginning with 'b'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; XFAIL: *
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'c'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'd'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'i'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'm'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'p'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 's'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sld_b_ARG2 = global i32 10, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; There are lots of these so this covers those beginning with 'v'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; use the result as a third operand.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll Fri Nov 15 05:04:16 2013
@@ -3,6 +3,7 @@
; operands had.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll Fri Nov 15 05:04:16 2013
@@ -3,6 +3,8 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck -check-prefix=MIPS32 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
+; RUN: FileCheck -check-prefix=MIPS32 %s
@llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_splat_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; use the result as a third operand.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; use the result as a third operand and perform fixed-point operations.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; 3RF instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; take an integer as an operand.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; produce an integer as a result.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/arithmetic.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: add_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/arithmetic_float.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: add_v4f32:
Modified: llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll Fri Nov 15 05:04:16 2013
@@ -22,8 +22,8 @@ define void @const_v16i8() nounwind {
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo(
- store volatile <16 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2>, <16 x i8>*@v16i8
- ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 258
+ store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
+ ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 256
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
; MIPS32-DAG: lui [[R2:\$[0-9]+]], 258
Modified: llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
@v2f64 = global <2 x double> <double 0.0, double 0.0>
Copied: llvm/trunk/test/CodeGen/Mips/msa/basic_operations_little.ll (from r194796, llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/basic_operations_little.ll?p2=llvm/trunk/test/CodeGen/Mips/msa/basic_operations_little.ll&p1=llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll&r1=194796&r2=194806&rev=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/basic_operations_little.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,6 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
+; This test will be merged back into basic_operations.ll once FileCheck accepts multiple prefixes.
+
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
@v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0>
@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
@@ -22,12 +24,12 @@ define void @const_v16i8() nounwind {
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo(
- store volatile <16 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2>, <16 x i8>*@v16i8
- ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 258
+ store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
+ ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
- ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 258
- ; MIPS32-DAG: ori [[R2]], [[R2]], 772
+ ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 1027
+ ; MIPS32-DAG: ori [[R2]], [[R2]], 513
; MIPS32-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
@@ -53,8 +55,8 @@ define void @const_v8i16() nounwind {
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 4
store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16
- ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 1
- ; MIPS32-DAG: ori [[R2]], [[R2]], 2
+ ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 2
+ ; MIPS32-DAG: ori [[R2]], [[R2]], 1
; MIPS32-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
@@ -143,13 +145,13 @@ define void @nonconst_v16i8(i8 %a, i8 %b
; MIPS32-DAG: insert.b [[R1]][1], $5
; MIPS32-DAG: insert.b [[R1]][2], $6
; MIPS32-DAG: insert.b [[R1]][3], $7
- ; MIPS32-DAG: lbu [[R2:\$[0-9]+]], 19($sp)
+ ; MIPS32-DAG: lbu [[R2:\$[0-9]+]], 16($sp)
; MIPS32-DAG: insert.b [[R1]][4], [[R2]]
- ; MIPS32-DAG: lbu [[R3:\$[0-9]+]], 23($sp)
+ ; MIPS32-DAG: lbu [[R3:\$[0-9]+]], 20($sp)
; MIPS32-DAG: insert.b [[R1]][5], [[R3]]
- ; MIPS32-DAG: lbu [[R4:\$[0-9]+]], 27($sp)
+ ; MIPS32-DAG: lbu [[R4:\$[0-9]+]], 24($sp)
; MIPS32-DAG: insert.b [[R1]][6], [[R4]]
- ; MIPS32-DAG: lbu [[R5:\$[0-9]+]], 31($sp)
+ ; MIPS32-DAG: lbu [[R5:\$[0-9]+]], 28($sp)
; MIPS32-DAG: insert.b [[R1]][7], [[R5]]
; MIPS32-DAG: insert.b [[R1]][8], [[R5]]
; MIPS32-DAG: insert.b [[R1]][9], [[R5]]
@@ -181,13 +183,13 @@ define void @nonconst_v8i16(i16 %a, i16
; MIPS32-DAG: insert.h [[R1]][1], $5
; MIPS32-DAG: insert.h [[R1]][2], $6
; MIPS32-DAG: insert.h [[R1]][3], $7
- ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 18($sp)
+ ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 16($sp)
; MIPS32-DAG: insert.h [[R1]][4], [[R2]]
- ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 22($sp)
+ ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 20($sp)
; MIPS32-DAG: insert.h [[R1]][5], [[R2]]
- ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 26($sp)
+ ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 24($sp)
; MIPS32-DAG: insert.h [[R1]][6], [[R2]]
- ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 30($sp)
+ ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 28($sp)
; MIPS32-DAG: insert.h [[R1]][7], [[R2]]
store volatile <8 x i16> %8, <8 x i16>*@v8i16
Modified: llvm/trunk/test/CodeGen/Mips/msa/bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bit.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bit.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bit.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,11 @@
+; Both endians should emit the same output for immediate instructions.
+; This is not currently true.
+; XFAIL: *
+
; Test the MSA intrinsics that are encoded with the BIT instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll Fri Nov 15 05:04:16 2013
@@ -1,7 +1,7 @@
; Test the bitcast operation for big-endian and little-endian.
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
define void @v16i8_to_v16i8(<16 x i8>* %src, <16 x i8>* %dst) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: and_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/compare.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/compare.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/compare.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: ceq_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/compare_float.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; are element extraction operations.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_copy_s_b_RES = global i32 0, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_cxcmsa.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; instruction format).
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define i32 @msa_ir_cfcmsa_test() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_insert_b_ARG3 = global i32 27, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_move.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; format).
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll Fri Nov 15 05:04:16 2013
@@ -1,7 +1,12 @@
+; Both endians should emit the same output for immediate instructions.
+; This is not currently true.
+; XFAIL: *
+
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are either shifts or slides.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sldi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Added: llvm/trunk/test/CodeGen/Mips/msa/endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/endian.ll?rev=194806&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/endian.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/msa/endian.ll Fri Nov 15 05:04:16 2013
@@ -0,0 +1,107 @@
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
+
+ at v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ at v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ at v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+ at v2i64 = global <2 x i64> <i64 0, i64 0>
+
+define void @const_v16i8() nounwind {
+ ; LITENDIAN: .byte 0
+ ; LITENDIAN: .byte 1
+ ; LITENDIAN: .byte 2
+ ; LITENDIAN: .byte 3
+ ; LITENDIAN: .byte 4
+ ; LITENDIAN: .byte 5
+ ; LITENDIAN: .byte 6
+ ; LITENDIAN: .byte 7
+ ; LITENDIAN: .byte 8
+ ; LITENDIAN: .byte 9
+ ; LITENDIAN: .byte 10
+ ; LITENDIAN: .byte 11
+ ; LITENDIAN: .byte 12
+ ; LITENDIAN: .byte 13
+ ; LITENDIAN: .byte 14
+ ; LITENDIAN: .byte 15
+ ; LITENDIAN: const_v16i8:
+ ; BIGENDIAN: .byte 0
+ ; BIGENDIAN: .byte 1
+ ; BIGENDIAN: .byte 2
+ ; BIGENDIAN: .byte 3
+ ; BIGENDIAN: .byte 4
+ ; BIGENDIAN: .byte 5
+ ; BIGENDIAN: .byte 6
+ ; BIGENDIAN: .byte 7
+ ; BIGENDIAN: .byte 8
+ ; BIGENDIAN: .byte 9
+ ; BIGENDIAN: .byte 10
+ ; BIGENDIAN: .byte 11
+ ; BIGENDIAN: .byte 12
+ ; BIGENDIAN: .byte 13
+ ; BIGENDIAN: .byte 14
+ ; BIGENDIAN: .byte 15
+ ; BIGENDIAN: const_v16i8:
+
+ store volatile <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8>*@v16i8
+
+ ret void
+}
+
+define void @const_v8i16() nounwind {
+ ; LITENDIAN: .2byte 0
+ ; LITENDIAN: .2byte 1
+ ; LITENDIAN: .2byte 2
+ ; LITENDIAN: .2byte 3
+ ; LITENDIAN: .2byte 4
+ ; LITENDIAN: .2byte 5
+ ; LITENDIAN: .2byte 6
+ ; LITENDIAN: .2byte 7
+ ; LITENDIAN: const_v8i16:
+ ; BIGENDIAN: .2byte 0
+ ; BIGENDIAN: .2byte 1
+ ; BIGENDIAN: .2byte 2
+ ; BIGENDIAN: .2byte 3
+ ; BIGENDIAN: .2byte 4
+ ; BIGENDIAN: .2byte 5
+ ; BIGENDIAN: .2byte 6
+ ; BIGENDIAN: .2byte 7
+ ; BIGENDIAN: const_v8i16:
+
+ store volatile <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, <8 x i16>*@v8i16
+
+ ret void
+}
+
+define void @const_v4i32() nounwind {
+ ; LITENDIAN: .4byte 0
+ ; LITENDIAN: .4byte 1
+ ; LITENDIAN: .4byte 2
+ ; LITENDIAN: .4byte 3
+ ; LITENDIAN: const_v4i32:
+ ; BIGENDIAN: .4byte 0
+ ; BIGENDIAN: .4byte 1
+ ; BIGENDIAN: .4byte 2
+ ; BIGENDIAN: .4byte 3
+ ; BIGENDIAN: const_v4i32:
+
+ store volatile <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>*@v4i32
+
+ ret void
+}
+
+define void @const_v2i64() nounwind {
+ ; LITENDIAN: .4byte 1
+ ; LITENDIAN: .4byte 0
+ ; LITENDIAN: .4byte 2
+ ; LITENDIAN: .4byte 0
+ ; LITENDIAN: const_v2i64:
+ ; BIGENDIAN: .4byte 0
+ ; BIGENDIAN: .4byte 1
+ ; BIGENDIAN: .4byte 0
+ ; BIGENDIAN: .4byte 2
+ ; BIGENDIAN: const_v2i64:
+
+ store volatile <2 x i64> <i64 1, i64 2>, <2 x i64>*@v2i64
+
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/Mips/msa/i10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i10.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i10.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i10.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,7 @@
; Test the MSA intrinsics that are encoded with the I10 instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll Fri Nov 15 05:04:16 2013
@@ -1,7 +1,12 @@
+; Both endians should emit the same output for immediate instructions.
+; This is not currently true.
+; XFAIL: *
+
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'a'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,8 @@
; There are lots of these so this covers those beginning with 'b'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
+; XFAIL: *
@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll Fri Nov 15 05:04:16 2013
@@ -1,7 +1,12 @@
+; Both endians should emit the same output for immediate instructions.
+; This is not currently true.
+; XFAIL: *
+
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'c'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceqi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll Fri Nov 15 05:04:16 2013
@@ -1,7 +1,12 @@
+; Both endians should emit the same output for immediate instructions.
+; This is not currently true.
+; XFAIL: *
+
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'm'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maxi_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll Fri Nov 15 05:04:16 2013
@@ -1,7 +1,12 @@
+; Both endians should emit the same output for immediate instructions.
+; This is not currently true.
+; XFAIL: *
+
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 's'
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_subvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; are loads or stores.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i8.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i8.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i8.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,7 @@
; Test the MSA intrinsics that are encoded with the I8 instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll Fri Nov 15 05:04:16 2013
@@ -1,5 +1,7 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
; This test originally failed for MSA with a
; `Opc && "Cannot copy registers"' assertion.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll Fri Nov 15 05:04:16 2013
@@ -1,5 +1,7 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
; This test originally failed to select instructions for extract_vector_elt for
; v4f32 on MSA.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll Fri Nov 15 05:04:16 2013
@@ -1,5 +1,7 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
; This test originally failed for MSA with a
; `Num < NumOperands && "Invalid child # of SDNode!"' assertion.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll Fri Nov 15 05:04:16 2013
@@ -1,5 +1,7 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
; This test originally failed to select instructions for extract_vector_elt for
; v2f64 on MSA.
Modified: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll Fri Nov 15 05:04:16 2013
@@ -1,5 +1,7 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
; This test originally failed to select code for a truncstore of a
; build_vector.
Modified: llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/shuffle.ll Fri Nov 15 05:04:16 2013
@@ -1,4 +1,5 @@
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: vshf_v16i8_0:
Modified: llvm/trunk/test/CodeGen/Mips/msa/spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/spill.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/spill.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/spill.ll Fri Nov 15 05:04:16 2013
@@ -2,6 +2,7 @@
; to have 33 live MSA registers simultaneously
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll?rev=194806&r1=194805&r2=194806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/vecs10.ll Fri Nov 15 05:04:16 2013
@@ -1,6 +1,7 @@
; Test the MSA intrinsics that are encoded with the VECS10 instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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