[llvm] r194684 - Add a comment
Matt Arsenault
Matthew.Arsenault at amd.com
Thu Nov 14 00:06:38 PST 2013
Author: arsenm
Date: Thu Nov 14 02:06:38 2013
New Revision: 194684
URL: http://llvm.org/viewvc/llvm-project?rev=194684&view=rev
Log:
Add a comment
Modified:
llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=194684&r1=194683&r2=194684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Thu Nov 14 02:06:38 2013
@@ -440,7 +440,9 @@ void SIInstrInfo::legalizeOperands(Machi
// Legalize VOP2
if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
MachineOperand &Src1 = MI->getOperand(Src1Idx);
- // Legalize VOP2 instructions where src1 is not a VGPR.
+
+ // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
+ // be the first operand, and there can only be one.
if (Src1.isImm() || Src1.isFPImm() ||
(Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
if (MI->isCommutable()) {
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