[llvm] r194569 - Support for microMIPS trap instruction with immediate operands.
Zoran Jovanovic
zoran.jovanovic at imgtec.com
Wed Nov 13 05:15:04 PST 2013
Author: zjovanovic
Date: Wed Nov 13 07:15:03 2013
New Revision: 194569
URL: http://llvm.org/viewvc/llvm-project?rev=194569&view=rev
Log:
Support for microMIPS trap instruction with immediate operands.
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
llvm/trunk/test/MC/Mips/micromips-trap-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td Wed Nov 13 07:15:03 2013
@@ -290,3 +290,15 @@ class TEQ_FM_MM<bits<6> funct> : MMArch
let Inst{11-6} = funct;
let Inst{5-0} = 0x3c;
}
+
+class TEQI_FM_MM<bits<5> funct> : MMArch {
+ bits<5> rs;
+ bits<16> imm16;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x10;
+ let Inst{25-21} = funct;
+ let Inst{20-16} = rs;
+ let Inst{15-0} = imm16;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed Nov 13 07:15:03 2013
@@ -209,4 +209,11 @@ let DecoderNamespace = "MicroMips", Pred
def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
+
+ def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
+ def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
+ def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
+ def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
+ def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
+ def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Nov 13 07:15:03 2013
@@ -468,7 +468,7 @@ class TEQ_FM<bits<6> funct> : StdArch {
let Inst{5-0} = funct;
}
-class TEQI_FM<bits<5> funct> {
+class TEQI_FM<bits<5> funct> : StdArch {
bits<5> rs;
bits<16> imm16;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Nov 13 07:15:03 2013
@@ -663,7 +663,7 @@ class TEQ_FT<string opstr, RegisterOpera
class TEQI_FT<string opstr, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
- !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
+ !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
// Mul, Div
class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
list<Register> DefRegs> :
@@ -971,12 +971,12 @@ def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
-def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
-def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
-def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
-def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
-def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
-def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
+def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
+def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
+def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
+def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
+def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
+def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips.txt?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips.txt Wed Nov 13 07:15:03 2013
@@ -267,3 +267,21 @@
# CHECK: tne $8, $9, 0
0x01 0x28 0x0c 0x3c
+
+# CHECK: teqi $9, 17767
+0x41,0xc9,0x45,0x67
+
+# CHECK: tgei $9, 17767
+0x41 0x29 0x45 0x67
+
+# CHECK: tgeiu $9, 17767
+0x41 0x69 0x45 0x67
+
+# CHECK: tlti $9, 17767
+0x41 0x09 0x45 0x67
+
+# CHECK: tltiu $9, 17767
+0x41 0x49 0x45 0x67
+
+# CHECK: tnei $9, 17767
+0x41 0x89 0x45 0x67
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt Wed Nov 13 07:15:03 2013
@@ -267,3 +267,21 @@
# CHECK: tne $8, $9, 0
0x28 0x01 0x3c 0x0c
+
+# CHECK: teqi $9, 17767
+0xc9 0x41 0x67 0x45
+
+# CHECK: tgei $9, 17767
+0x29 0x41 0x67 0x45
+
+# CHECK: tgeiu $9, 17767
+0x69 0x41 0x67 0x45
+
+# CHECK: tlti $9, 17767
+0x09 0x41 0x67 0x45
+
+# CHECK: tltiu $9, 17767
+0x49 0x41 0x67 0x45
+
+# CHECK: tnei $9, 17767
+0x89 0x41 0x67 0x45
Modified: llvm/trunk/test/MC/Mips/micromips-trap-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-trap-instructions.s?rev=194569&r1=194568&r2=194569&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-trap-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-trap-instructions.s Wed Nov 13 07:15:03 2013
@@ -15,6 +15,12 @@
# CHECK-EL: tlt $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x08]
# CHECK-EL: tltu $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x0a]
# CHECK-EL: tne $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x0c]
+# CHECK-EL: teqi $9, 17767 # encoding: [0xc9,0x41,0x67,0x45]
+# CHECK-EL: tgei $9, 17767 # encoding: [0x29,0x41,0x67,0x45]
+# CHECK-EL: tgeiu $9, 17767 # encoding: [0x69,0x41,0x67,0x45]
+# CHECK-EL: tlti $9, 17767 # encoding: [0x09,0x41,0x67,0x45]
+# CHECK-EL: tltiu $9, 17767 # encoding: [0x49,0x41,0x67,0x45]
+# CHECK-EL: tnei $9, 17767 # encoding: [0x89,0x41,0x67,0x45]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -24,9 +30,21 @@
# CHECK-EB: tlt $8, $9, 0 # encoding: [0x01,0x28,0x08,0x3c]
# CHECK-EB: tltu $8, $9, 0 # encoding: [0x01,0x28,0x0a,0x3c]
# CHECK-EB: tne $8, $9, 0 # encoding: [0x01,0x28,0x0c,0x3c]
+# CHECK-EB: teqi $9, 17767 # encoding: [0x41,0xc9,0x45,0x67]
+# CHECK-EB: tgei $9, 17767 # encoding: [0x41,0x29,0x45,0x67]
+# CHECK-EB: tgeiu $9, 17767 # encoding: [0x41,0x69,0x45,0x67]
+# CHECK-EB: tlti $9, 17767 # encoding: [0x41,0x09,0x45,0x67]
+# CHECK-EB: tltiu $9, 17767 # encoding: [0x41,0x49,0x45,0x67]
+# CHECK-EB: tnei $9, 17767 # encoding: [0x41,0x89,0x45,0x67]
teq $8, $9, 0
tge $8, $9, 0
tgeu $8, $9, 0
tlt $8, $9, 0
tltu $8, $9, 0
tne $8, $9, 0
+ teqi $9, 17767
+ tgei $9, 17767
+ tgeiu $9, 17767
+ tlti $9, 17767
+ tltiu $9, 17767
+ tnei $9, 17767
More information about the llvm-commits
mailing list