[PATCH] Added aliases for SIMD copy instrucitons
Kevin Qin
kevinqindev at gmail.com
Wed Nov 13 02:34:21 PST 2013
Hi,
This patch added aliases for SIMD copy instrucitons and set unspecified bits of DUP and INS to zero as ARMARM request. please review, thanks.
http://llvm-reviews.chandlerc.com/D2167
Files:
lib/Target/AArch64/AArch64InstrNEON.td
test/MC/AArch64/neon-simd-copy.s
Index: lib/Target/AArch64/AArch64InstrNEON.td
===================================================================
--- lib/Target/AArch64/AArch64InstrNEON.td
+++ lib/Target/AArch64/AArch64InstrNEON.td
@@ -4834,21 +4834,6 @@
let PrintMethod = "printUImmHexOperand";
}
-class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
- RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
- : NeonI_copy<0b1, 0b0, 0b0011,
- (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
- asmop # "\t$Rd." # Res # "[$Imm], $Rn",
- [(set (ResTy VPR128:$Rd),
- (ResTy (vector_insert
- (ResTy VPR128:$src),
- (OpTy OpGPR:$Rn),
- (OpImm:$Imm))))],
- NoItinerary> {
- bits<4> Imm;
- let Constraints = "$src = $Rd";
-}
-
// Bitwise Extract
class NeonI_Extract<bit q, bits<2> op2, string asmop,
string OpS, RegisterOperand OpVPR, Operand OpImm>
@@ -5652,6 +5637,21 @@
// End of implementation for instruction class (3V Elem)
+class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
+ RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
+ : NeonI_copy<0b1, 0b0, 0b0011,
+ (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
+ asmop # "\t$Rd." # Res # "[$Imm], $Rn",
+ [(set (ResTy VPR128:$Rd),
+ (ResTy (vector_insert
+ (ResTy VPR128:$src),
+ (OpTy OpGPR:$Rn),
+ (OpImm:$Imm))))],
+ NoItinerary> {
+ bits<4> Imm;
+ let Constraints = "$src = $Rd";
+}
+
//Insert element (vector, from main)
def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
neon_uimm4_bare> {
@@ -5670,6 +5670,15 @@
let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
}
+def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
+ (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
+def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
+ (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
+def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
+ (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
+def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
+ (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
+
class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
RegisterClass OpGPR, ValueType OpTy,
Operand OpImm, Instruction INS>
@@ -5709,19 +5718,32 @@
}
def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
- let Inst{14-12} = {Immn{2}, Immn{1}, Immn{0}};
- // bit 11 is unspecified.
+ let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
+ // bit 11 is unspecified, but should be set to zero.
}
def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
- let Inst{14-13} = {Immn{1}, Immn{0}};
- // bits 11-12 are unspecified.
+ let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
+ // bits 11-12 are unspecified, but should be set to zero.
}
def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
- let Inst{14} = Immn{0};
- // bits 11-13 are unspecified.
-}
+ let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
+ // bits 11-13 are unspecified, but should be set to zero.
+}
+
+def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
+ (INSELb VPR128:$Rd, VPR128:$Rn,
+ neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
+def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
+ (INSELh VPR128:$Rd, VPR128:$Rn,
+ neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
+def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
+ (INSELs VPR128:$Rd, VPR128:$Rn,
+ neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
+def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
+ (INSELd VPR128:$Rd, VPR128:$Rn,
+ neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
ValueType MidTy, Operand StImm, Operand NaImm,
@@ -5943,6 +5965,11 @@
let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
}
+def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
+ (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
+def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
+ (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
+
class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
Operand StImm, Operand NaImm,
Instruction SMOVI>
@@ -6145,37 +6172,38 @@
NoItinerary>;
def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
- let Inst{16} = 0b1;
- // bits 17-19 are unspecified.
+ let Inst{20-16} = 0b00001;
+ // bits 17-20 are unspecified, but should be set to zero.
}
def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
- let Inst{17-16} = 0b10;
- // bits 18-19 are unspecified.
+ let Inst{20-16} = 0b00010;
+ // bits 18-20 are unspecified, but should be set to zero.
}
def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
- let Inst{18-16} = 0b100;
- // bit 19 is unspecified.
+ let Inst{20-16} = 0b00100;
+ // bits 19-20 are unspecified, but should be set to zero.
}
def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
- let Inst{19-16} = 0b1000;
+ let Inst{20-16} = 0b01000;
+ // bit 20 is unspecified, but should be set to zero.
}
def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
- let Inst{16} = 0b1;
- // bits 17-19 are unspecified.
+ let Inst{20-16} = 0b00001;
+ // bits 17-20 are unspecified, but should be set to zero.
}
def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
- let Inst{17-16} = 0b10;
- // bits 18-19 are unspecified.
+ let Inst{20-16} = 0b00010;
+ // bits 18-20 are unspecified, but should be set to zero.
}
def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
- let Inst{18-16} = 0b100;
- // bit 19 is unspecified.
+ let Inst{20-16} = 0b00100;
+ // bits 19-20 are unspecified, but should be set to zero.
}
// patterns for CONCAT_VECTORS
Index: test/MC/AArch64/neon-simd-copy.s
===================================================================
--- test/MC/AArch64/neon-simd-copy.s
+++ test/MC/AArch64/neon-simd-copy.s
@@ -57,7 +57,7 @@
// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e]
// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e]
-// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x5e,0x1c,0x6e]
+// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e]
// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e]
//------------------------------------------------------------------------------
@@ -91,11 +91,11 @@
dup v5.2d, x0
// CHECK: dup v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e]
-// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x0a,0x0e]
-// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x14,0x0e]
+// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e]
+// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e]
// CHECK: dup v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e]
-// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x0a,0x4e]
-// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x14,0x4e]
+// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e]
+// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e]
// CHECK: dup v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e]
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