[PATCH] R600: Make dot_4 instructions predicable

[Tom Stellard]

On Tue, Nov 12, 2013 at 12:24:53PM -0800, Vincent Lejeune wrote:
> This fixes a shader from Shadertoy website.
> 
> http://llvm-reviews.chandlerc.com/D2155



> 
> Files:
>   lib/Target/R600/R600InstrInfo.cpp
>   test/CodeGen/R600/predicate-dp4.ll
> 
> Index: lib/Target/R600/R600InstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/R600InstrInfo.cpp
> +++ lib/Target/R600/R600InstrInfo.cpp
> @@ -1005,6 +1005,20 @@
>      return true;
>    }
>  
> +  if (MI->getOpcode() == AMDGPU::DOT_4) {
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
> +        .setReg(Pred[2].getReg());
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
> +        .setReg(Pred[2].getReg());
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
> +        .setReg(Pred[2].getReg());
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
> +        .setReg(Pred[2].getReg());
> +    MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
> +    MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
> +    return true;
> +  }
> +
>    if (PIdx != -1) {
>      MachineOperand &PMO = MI->getOperand(PIdx);
>      PMO.setReg(Pred[2].getReg());
> @@ -1255,6 +1269,11 @@
>      AMDGPU::OpName::src1_sel,
>    };
>  
> +  MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
> +      getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
> +  MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
> +      .setReg(MO.getReg());
> +
>    for (unsigned i = 0; i < 14; i++) {
>      MachineOperand &MO = MI->getOperand(
>          getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
> Index: test/CodeGen/R600/predicate-dp4.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/predicate-dp4.ll
> @@ -0,0 +1,27 @@
> +;RUN: llc < %s -march=r600 -mcpu=cayman
> +
> +; CHECK-label: @main

Capitalize label here for consistency with other tests: CHECK-LABEL

With that fix:

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

> +; CHECK: PRED_SETE_INT * Pred,
> +; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one
> +define void @main(<4 x float> inreg) #0 {
> +main_body:
> +  %1 = extractelement <4 x float> %0, i32 0
> +  %2 = bitcast float %1 to i32
> +  %3 = icmp eq i32 %2, 0
> +  br i1 %3, label %IF, label %ENDIF
> +
> +IF:                                             ; preds = %main_body
> +  %4 = call float @llvm.AMDGPU.dp4(<4 x float> %0, <4 x float> %0)
> +  br label %ENDIF
> +
> +ENDIF:                                            ; preds = %IF, %main_body
> +  %5 = phi float [%4, %IF], [0.000000e+00, %main_body]
> +  %6 = insertelement <4 x float> undef, float %5, i32 0
> +  call void @llvm.R600.store.swizzle(<4 x float> %6, i32 0, i32 0)
> +  ret void
> +}
> +
> +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
> +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
> +attributes #1 = { readnone }
> +attributes #0 = { "ShaderType"="0" }
> \ No newline at end of file

> Index: lib/Target/R600/R600InstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/R600InstrInfo.cpp
> +++ lib/Target/R600/R600InstrInfo.cpp
> @@ -1005,6 +1005,20 @@
>      return true;
>    }
>  
> +  if (MI->getOpcode() == AMDGPU::DOT_4) {
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
> +        .setReg(Pred[2].getReg());
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
> +        .setReg(Pred[2].getReg());
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
> +        .setReg(Pred[2].getReg());
> +    MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
> +        .setReg(Pred[2].getReg());
> +    MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
> +    MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
> +    return true;
> +  }
> +
>    if (PIdx != -1) {
>      MachineOperand &PMO = MI->getOperand(PIdx);
>      PMO.setReg(Pred[2].getReg());
> @@ -1255,6 +1269,11 @@
>      AMDGPU::OpName::src1_sel,
>    };
>  
> +  MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
> +      getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
> +  MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
> +      .setReg(MO.getReg());
> +
>    for (unsigned i = 0; i < 14; i++) {
>      MachineOperand &MO = MI->getOperand(
>          getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
> Index: test/CodeGen/R600/predicate-dp4.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/predicate-dp4.ll
> @@ -0,0 +1,27 @@
> +;RUN: llc < %s -march=r600 -mcpu=cayman
> +
> +; CHECK-label: @main
> +; CHECK: PRED_SETE_INT * Pred,
> +; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one
> +define void @main(<4 x float> inreg) #0 {
> +main_body:
> +  %1 = extractelement <4 x float> %0, i32 0
> +  %2 = bitcast float %1 to i32
> +  %3 = icmp eq i32 %2, 0
> +  br i1 %3, label %IF, label %ENDIF
> +
> +IF:                                             ; preds = %main_body
> +  %4 = call float @llvm.AMDGPU.dp4(<4 x float> %0, <4 x float> %0)
> +  br label %ENDIF
> +
> +ENDIF:                                            ; preds = %IF, %main_body
> +  %5 = phi float [%4, %IF], [0.000000e+00, %main_body]
> +  %6 = insertelement <4 x float> undef, float %5, i32 0
> +  call void @llvm.R600.store.swizzle(<4 x float> %6, i32 0, i32 0)
> +  ret void
> +}
> +
> +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
> +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
> +attributes #1 = { readnone }
> +attributes #0 = { "ShaderType"="0" }
> \ No newline at end of file

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