[PATCH] ARMAsmParser permitted p10 and p11 as operands for coprocessor instructions, resulting in ambiguous encodings

[Artyom Skrobov]

Hello,

CP10/11 are reserved for FP/NEON operations, and are invalid as operands for
the generic coprocessor instructions.

They are correctly treated as invalid operands when decoding the coprocessor
instructions, but the assembler permits them nevertheless, leading to
multiple MCInsts sharing the same encoding:

$ llvm-mc -triple armv7 -show-encoding
mcr p10, #0, r0, c0, c0, #0
	.text
	mcr	p10, #0, r0, c0, c0, #0 @ encoding: [0x10,0x0a,0x00,0xee]
$ llvm-mc -triple armv7 -show-encoding -disassemble
[0x10,0x0a,0x00,0xee]
	.text
	vmov	s0, r0                  @ encoding: [0x10,0x0a,0x00,0xee]

Our patch fixes ARMAsmParser to disallow p10 and p11 as coprocessor
operands. The patch also updates the tests that tried to assemble these
invalid coprocessor instructions.

OK to commit?
-------------- next part --------------
A non-text attachment was scrubbed...
Name: cp10_11_asm.patch
Type: application/octet-stream
Size: 9766 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20131107/530b35ce/attachment.obj>