[llvm] r193859 - [ARM] Add Virtualization subtarget feature and more build attributes in this area
Bradley Smith
bradley.smith at arm.com
Fri Nov 1 06:27:36 PDT 2013
Author: brasmi01
Date: Fri Nov 1 08:27:35 2013
New Revision: 193859
URL: http://llvm.org/viewvc/llvm-project?rev=193859&view=rev
Log:
[ARM] Add Virtualization subtarget feature and more build attributes in this area
Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.
Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.
Added:
llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s
Removed:
llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=193859&r1=193858&r2=193859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Fri Nov 1 08:27:35 2013
@@ -119,6 +119,12 @@ def FeatureDSPThumb2 : SubtargetFeature<
def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
"Supports Multiprocessing extension">;
+// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
+def FeatureVirtualization : SubtargetFeature<"virtualization",
+ "HasVirtualization", "true",
+ "Supports Virtualization extension",
+ [FeatureHWDiv, FeatureHWDivARM]>;
+
// M-series ISA
def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
"Is microcontroller profile ('M' series)">;
@@ -159,7 +165,8 @@ def HasV7Ops : SubtargetFeature<"v7",
[HasV6T2Ops, FeaturePerfMon]>;
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
"Support ARM v8 instructions",
- [HasV7Ops]>;
+ [HasV7Ops, FeatureVirtualization,
+ FeatureMP]>;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@@ -198,17 +205,17 @@ def ProcA15 : SubtargetFeature<"a15
[FeatureT2XtPk, FeatureVFP4,
FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureAvoidPartialCPSR,
- FeatureTrustZone]>;
+ FeatureTrustZone, FeatureVirtualization]>;
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors",
- [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
+ [FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto, FeatureCRC]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors",
- [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
+ [FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto, FeatureCRC]>;
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=193859&r1=193858&r2=193859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Nov 1 08:27:35 2013
@@ -703,6 +703,9 @@ void ARMAsmPrinter::emitAttributes() {
// FIXME: Should we signal R9 usage?
+ if (Subtarget->hasMPExtension())
+ ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
+
if (Subtarget->hasDivide()) {
// Check if hardware divide is only available in thumb2 or ARM as well.
ATS.emitAttribute(ARMBuildAttrs::DIV_use,
@@ -710,6 +713,16 @@ void ARMAsmPrinter::emitAttributes() {
ARMBuildAttrs::AllowDIVIfExists);
}
+ if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
+ ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
+ ARMBuildAttrs::AllowTZVirtualization);
+ else if (Subtarget->hasTrustZone())
+ ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
+ ARMBuildAttrs::AllowTZ);
+ else if (Subtarget->hasVirtualization())
+ ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
+ ARMBuildAttrs::AllowVirtualization);
+
ATS.finishAttributeSection();
}
Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=193859&r1=193858&r2=193859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Fri Nov 1 08:27:35 2013
@@ -144,11 +144,19 @@ namespace ARMBuildAttrs {
BaseAAPCS = 0,
HardFPAAPCS = 1,
+ // Tag_MPextension_use, (=42), uleb128
+ AllowMP = 1, // Allow use of MP extensions
+
// Tag_DIV_use, (=44), uleb128
AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no info exists.
DisallowDIV = 1, // Hardware divide explicitly disallowed
- AllowDIVExt = 2 // Allow hardware divide as optional architecture extension above
+ AllowDIVExt = 2, // Allow hardware divide as optional architecture extension above
// the base arch specified by Tag_CPU_arch and Tag_CPU_arch_profile.
+
+ // Tag_Virtualization_use, (=68), uleb128
+ AllowTZ = 1,
+ AllowVirtualization = 2,
+ AllowTZVirtualization = 3
};
} // namespace ARMBuildAttrs
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=193859&r1=193858&r2=193859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Fri Nov 1 08:27:35 2013
@@ -108,6 +108,7 @@ void ARMSubtarget::initializeEnvironment
AvoidMOVsShifterOperand = false;
HasRAS = false;
HasMPExtension = false;
+ HasVirtualization = false;
FPOnlySP = false;
HasPerfMon = false;
HasTrustZone = false;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=193859&r1=193858&r2=193859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Nov 1 08:27:35 2013
@@ -150,6 +150,10 @@ protected:
/// extension (ARMv7 only).
bool HasMPExtension;
+ /// HasVirtualization - True if the subtarget supports the Virtualization
+ /// extension.
+ bool HasVirtualization;
+
/// FPOnlySP - If true, the floating point unit only supports single
/// precision.
bool FPOnlySP;
@@ -260,6 +264,7 @@ public:
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
bool hasCRC() const { return HasCRC; }
+ bool hasVirtualization() const { return HasVirtualization; }
bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; }
Modified: llvm/trunk/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll?rev=193859&r1=193858&r2=193859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll Fri Nov 1 08:27:35 2013
@@ -14,6 +14,7 @@
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
@@ -28,6 +29,8 @@
; V6: .eabi_attribute 25, 1
; V6-NOT: .eabi_attribute 27
; V6-NOT: .eabi_attribute 28
+; V6-NOT: .eabi_attribute 42
+; V6-NOT: .eabi_attribute 68
; V6M: .eabi_attribute 6, 12
; V6M: .eabi_attribute 7, 77
@@ -37,6 +40,8 @@
; V6M: .eabi_attribute 25, 1
; V6M-NOT: .eabi_attribute 27
; V6M-NOT: .eabi_attribute 28
+; V6M-NOT: .eabi_attribute 42
+; V6M-NOT: .eabi_attribute 68
; ARM1156T2F-S: .cpu arm1156t2f-s
; ARM1156T2F-S: .eabi_attribute 6, 8
@@ -50,6 +55,8 @@
; ARM1156T2F-S: .eabi_attribute 25, 1
; ARM1156T2F-S-NOT: .eabi_attribute 27
; ARM1156T2F-S-NOT: .eabi_attribute 28
+; ARM1156T2F-S-NOT: .eabi_attribute 42
+; ARM1156T2F-S-NOT: .eabi_attribute 68
; V7M: .eabi_attribute 6, 10
; V7M: .eabi_attribute 7, 77
@@ -59,7 +66,9 @@
; V7M: .eabi_attribute 25, 1
; V7M-NOT: .eabi_attribute 27
; V7M-NOT: .eabi_attribute 28
+; V7M-NOT: .eabi_attribute 42
; V7M: .eabi_attribute 44, 0
+; V7M-NOT: .eabi_attribute 68
; V7: .syntax unified
; V7: .eabi_attribute 6, 10
@@ -70,6 +79,8 @@
; V7: .eabi_attribute 25, 1
; V7-NOT: .eabi_attribute 27
; V7-NOT: .eabi_attribute 28
+; V7-NOT: .eabi_attribute 42
+; V7-NOT: .eabi_attribute 68
; V8: .syntax unified
; V8: .eabi_attribute 6, 14
@@ -109,6 +120,8 @@
; CORTEX-A9-SOFT: .eabi_attribute 25, 1
; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
; CORTEX-A9-SOFT-NOT: .eabi_attribute 28
+; CORTEX-A9-SOFT-NOT: .eabi_attribute 42
+; CORTEX-A9-SOFT: .eabi_attribute 68, 1
; CORTEX-A9-HARD: .cpu cortex-a9
; CORTEX-A9-HARD: .eabi_attribute 6, 10
@@ -123,6 +136,24 @@
; CORTEX-A9-HARD: .eabi_attribute 25, 1
; CORTEX-A9-HARD-NOT: .eabi_attribute 27
; CORTEX-A9-HARD: .eabi_attribute 28, 1
+; CORTEX-A9-HARD-NOT: .eabi_attribute 42
+; CORTEX-A9-HARD: .eabi_attribute 68, 1
+
+; CORTEX-A9-MP: .cpu cortex-a9-mp
+; CORTEX-A9-MP: .eabi_attribute 6, 10
+; CORTEX-A9-MP: .eabi_attribute 7, 65
+; CORTEX-A9-MP: .eabi_attribute 8, 1
+; CORTEX-A9-MP: .eabi_attribute 9, 2
+; CORTEX-A9-MP: .fpu neon
+; CORTEX-A9-MP: .eabi_attribute 20, 1
+; CORTEX-A9-MP: .eabi_attribute 21, 1
+; CORTEX-A9-MP: .eabi_attribute 23, 3
+; CORTEX-A9-MP: .eabi_attribute 24, 1
+; CORTEX-A9-MP: .eabi_attribute 25, 1
+; CORTEX-A9-NOT: .eabi_attribute 27
+; CORTEX-A9-NOT: .eabi_attribute 28
+; CORTEX-A9-MP: .eabi_attribute 42, 1
+; CORTEX-A9-MP: .eabi_attribute 68, 1
; CORTEX-A15: .cpu cortex-a15
; CORTEX-A15: .eabi_attribute 6, 10
@@ -135,9 +166,11 @@
; CORTEX-A15: .eabi_attribute 23, 3
; CORTEX-A15: .eabi_attribute 24, 1
; CORTEX-A15: .eabi_attribute 25, 1
+; CORTEX-A15: .eabi_attribute 42, 1
; CORTEX-A15: .eabi_attribute 44, 2
; CORTEX-A15-NOT: .eabi_attribute 27
; CORTEX-A15-NOT: .eabi_attribute 28
+; CORTEX-A15: .eabi_attribute 68, 3
; CORTEX-M0: .cpu cortex-m0
; CORTEX-M0: .eabi_attribute 6, 12
@@ -148,6 +181,8 @@
; CORTEX-M0: .eabi_attribute 25, 1
; CORTEX-M0-NOT: .eabi_attribute 27
; CORTEX-M0-NOT: .eabi_attribute 28
+; CORTEX-M0-NOT: .eabi_attribute 42
+; CORTEX-M0-NOT: .eabi_attribute 68
; CORTEX-M4-SOFT: .cpu cortex-m4
; CORTEX-M4-SOFT: .eabi_attribute 6, 13
@@ -162,7 +197,9 @@
; CORTEX-M4-SOFT: .eabi_attribute 25, 1
; CORTEX-M4-SOFT: .eabi_attribute 27, 1
; CORTEX-M4-SOFT-NOT: .eabi_attribute 28
+; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
; CORTEX-M4-SOFT: .eabi_attribute 44, 0
+; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
; CORTEX-M4-HARD: .cpu cortex-m4
; CORTEX-M4-HARD: .eabi_attribute 6, 13
@@ -177,12 +214,14 @@
; CORTEX-M4-HARD: .eabi_attribute 25, 1
; CORTEX-M4-HARD: .eabi_attribute 27, 1
; CORTEX-M4-HARD: .eabi_attribute 28, 1
+; CORTEX-M4-HARD-NOT: .eabi_attribute 42
; CORTEX-M4-HARD: .eabi_attribute 44, 0
+; CORTEX-M4-HRAD-NOT: .eabi_attribute 68
; CORTEX-R5: .cpu cortex-r5
; CORTEX-R5: .eabi_attribute 6, 10
; CORTEX-R5: .eabi_attribute 7, 82
-; CORTEX-R5: .eabi_attribute 8, 1
+; CORTEX-R5: .eabi_attribute 8, 1
; CORTEX-R5: .eabi_attribute 9, 2
; CORTEX-R5: .fpu vfpv3-d16
; CORTEX-R5: .eabi_attribute 20, 1
@@ -192,7 +231,9 @@
; CORTEX-R5: .eabi_attribute 25, 1
; CORTEX-R5: .eabi_attribute 27, 1
; CORTEX-R5-NOT: .eabi_attribute 28
+; CORTEX-R5-NOT: .eabi_attribute 42
; CORTEX-R5: .eabi_attribute 44, 2
+; CORTEX-R5-NOT: .eabi_attribute 68
; CORTEX-A53: .cpu cortex-a53
; CORTEX-A53: .eabi_attribute 6, 14
@@ -205,7 +246,9 @@
; CORTEX-A53: .eabi_attribute 25, 1
; CORTEX-A53-NOT: .eabi_attribute 27
; CORTEX-A53-NOT: .eabi_attribute 28
+; CORTEX-A53: .eabi_attribute 42, 1
; CORTEX-A53: .eabi_attribute 44, 2
+; CORTEX-A53: .eabi_attribute 68, 3
; CORTEX-A57: .cpu cortex-a57
; CORTEX-A57: .eabi_attribute 6, 14
@@ -218,7 +261,9 @@
; CORTEX-A57: .eabi_attribute 25, 1
; CORTEX-A57-NOT: .eabi_attribute 27
; CORTEX-A57-NOT: .eabi_attribute 28
+; CORTEX-A57: .eabi_attribute 42, 1
; CORTEX-A57: .eabi_attribute 44, 2
+; CORTEX-A57: .eabi_attribute 68, 3
define i32 @f(i64 %z) {
ret i32 0
Removed: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=193858&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (removed)
@@ -1,263 +0,0 @@
-; This tests that the expected ARM attributes are emitted.
-
-; RUN: llc < %s -mtriple=arm-linux-gnueabi -filetype=obj -o - \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=BASIC
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \
-; RUN: -mattr=-neon,-vfp3,+vfp2 -arm-reserve-r9 -filetype=obj -o - \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-A8
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V7
-; RUN: llc < %s -mtriple=armv8-linux-gnueabi -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8
-; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=Vt8
-; RUN: llc < %s -mtriple=armv8-linux-gnueabi \
-; RUN: -mattr=-neon,-crypto -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8-FPARMv8
-; RUN: llc < %s -mtriple=armv8-linux-gnueabi \
-; RUN: -mattr=-fp-armv8,-crypto -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8-NEON
-; RUN: llc < %s -mtriple=armv8-linux-gnueabi \
-; RUN: -mattr=-crypto -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8-FPARMv8-NEON
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-A9
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-A15
-; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-M0
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-M4
-; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -filetype=obj \
-; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-R5
-
-; BASIC: Section {
-; BASIC: Name: .ARM.attributes
-; BASIC-NEXT: Type: SHT_ARM_ATTRIBUTES
-; BASIC-NEXT: Flags [ (0x0)
-; BASIC-NEXT: ]
-; BASIC-NEXT: Address: 0x0
-; BASIC-NEXT: Offset: 0x3C
-; BASIC-NEXT: Size: 30
-; BASIC-NEXT: Link: 0
-; BASIC-NEXT: Info: 0
-; BASIC-NEXT: AddressAlignment: 1
-; BASIC-NEXT: EntrySize: 0
-; BASIC-NEXT: SectionData (
-; BASIC-NEXT: 0000: 411D0000 00616561 62690001 13000000
-; BASIC-NEXT: 0010: 06010801 14011501 17031801 1901
-; BASIC-NEXT: )
-
-; CORTEX-A8: Name: .ARM.attributes
-; CORTEX-A8-NEXT: Type: SHT_ARM_ATTRIBUTES
-; CORTEX-A8-NEXT: Flags [ (0x0)
-; CORTEX-A8-NEXT: ]
-; CORTEX-A8-NEXT: Address: 0x0
-; CORTEX-A8-NEXT: Offset: 0x3C
-; CORTEX-A8-NEXT: Size: 47
-; CORTEX-A8-NEXT: Link: 0
-; CORTEX-A8-NEXT: Info: 0
-; CORTEX-A8-NEXT: AddressAlignment: 1
-; CORTEX-A8-NEXT: EntrySize: 0
-; CORTEX-A8-NEXT: SectionData (
-; CORTEX-A8-NEXT: 0000: 412E0000 00616561 62690001 24000000
-; CORTEX-A8-NEXT: 0010: 05434F52 5445582D 41380006 0A074108
-; CORTEX-A8-NEXT: 0020: 0109020A 02140115 01170318 011901
-; CORTEX-A8-NEXT: )
-
-; V7: Name: .ARM.attributes
-; V7-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; V7-NEXT: Flags [ (0x0)
-; V7-NEXT: ]
-; V7-NEXT: Address: 0x0
-; V7-NEXT: Offset: 0x3C
-; V7-NEXT: Size: 36
-; V7-NEXT: Link: 0
-; V7-NEXT: Info: 0
-; V7-NEXT: AddressAlignment: 1
-; V7-NEXT: EntrySize: 0
-; V7-NEXT: SectionData (
-; V7-NEXT: 0000: 41230000 00616561 62690001 19000000
-; V7-NEXT: 0010: 060A0801 09020A03 0C011401 15011703
-; V7-NEXT: 0020: 18011901
-; V7-NEXT: )
-
-; V8: Name: .ARM.attributes
-; V8-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; V8-NEXT: Flags [ (0x0)
-; V8-NEXT: ]
-; V8-NEXT: Address: 0x0
-; V8-NEXT: Offset: 0x3C
-; V8-NEXT: Size: 38
-; V8-NEXT: Link: 0
-; V8-NEXT: Info: 0
-; V8-NEXT: AddressAlignment: 1
-; V8-NEXT: EntrySize: 0
-; V8-NEXT: SectionData (
-; V8-NEXT: 0000: 41250000 00616561 62690001 1B000000
-; V8-NEXT: 0010: 060E0801 09020A07 0C031401 15011703
-; V8-NEXT: 0020: 18011901 2C02
-; V8-NEXT: )
-
-; Vt8: Name: .ARM.attributes
-; Vt8-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; Vt8-NEXT: Flags [ (0x0)
-; Vt8-NEXT: ]
-; Vt8-NEXT: Address: 0x0
-; Vt8-NEXT: Offset: 0x38
-; Vt8-NEXT: Size: 38
-; Vt8-NEXT: Link: 0
-; Vt8-NEXT: Info: 0
-; Vt8-NEXT: AddressAlignment: 1
-; Vt8-NEXT: EntrySize: 0
-; Vt8-NEXT: SectionData (
-; Vt8-NEXT: 0000: 41250000 00616561 62690001 1B000000
-; Vt8-NEXT: 0010: 060E0801 09020A07 0C031401 15011703
-; Vt8-NEXT: 0020: 18011901 2C02
-; Vt8-NEXT: )
-
-
-; V8-FPARMv8: Name: .ARM.attributes
-; V8-FPARMv8-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; V8-FPARMv8-NEXT: Flags [ (0x0)
-; V8-FPARMv8-NEXT: ]
-; V8-FPARMv8-NEXT: Address: 0x0
-; V8-FPARMv8-NEXT: Offset: 0x3C
-; V8-FPARMv8-NEXT: Size: 36
-; V8-FPARMv8-NEXT: Link: 0
-; V8-FPARMv8-NEXT: Info: 0
-; V8-FPARMv8-NEXT: AddressAlignment: 1
-; V8-FPARMv8-NEXT: EntrySize: 0
-; V8-FPARMv8-NEXT: SectionData (
-; V8-FPARMv8-NEXT: 0000: 41230000 00616561 62690001 19000000
-; V8-FPARMv8-NEXT: 0010: 060E0801 09020A07 14011501 17031801
-; V8-FPARMv8-NEXT: 0020: 19012C02
-; V8-FPARMv8-NEXT: )
-
-
-; V8-NEON: Name: .ARM.attributes
-; V8-NEON-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; V8-NEON-NEXT: Flags [ (0x0)
-; V8-NEON-NEXT: ]
-; V8-NEON-NEXT: Address: 0x0
-; V8-NEON-NEXT: Offset: 0x3C
-; V8-NEON-NEXT: Size: 38
-; V8-NEON-NEXT: Link: 0
-; V8-NEON-NEXT: Info: 0
-; V8-NEON-NEXT: AddressAlignment: 1
-; V8-NEON-NEXT: EntrySize: 0
-; V8-NEON-NEXT: SectionData (
-; V8-NEON-NEXT: 0000: 41250000 00616561 62690001 1B000000
-; V8-NEON-NEXT: 0010: 060E0801 09020A05 0C031401 15011703
-; V8-NEON-NEXT: 0020: 18011901 2C02
-; V8-NEON-NEXT: )
-
-; V8-FPARMv8-NEON: Name: .ARM.attributes
-; V8-FPARMv8-NEON-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; V8-FPARMv8-NEON-NEXT: Flags [ (0x0)
-; V8-FPARMv8-NEON-NEXT: ]
-; V8-FPARMv8-NEON-NEXT: Address: 0x0
-; V8-FPARMv8-NEON-NEXT: Offset: 0x3C
-; V8-FPARMv8-NEON-NEXT: Size: 38
-; V8-FPARMv8-NEON-NEXT: Link: 0
-; V8-FPARMv8-NEON-NEXT: Info: 0
-; V8-FPARMv8-NEON-NEXT: AddressAlignment: 1
-; V8-FPARMv8-NEON-NEXT: EntrySize: 0
-; V8-FPARMv8-NEON-NEXT: SectionData (
-; V8-FPARMv8-NEON-NEXT: 0000: 41250000 00616561 62690001 1B000000
-; V8-FPARMv8-NEON-NEXT: 0010: 060E0801 09020A07 0C031401 15011703
-; V8-FPARMv8-NEON-NEXT: 0020: 18011901 2C02
-; V8-FPARMv8-NEON-NEXT: )
-
-; CORTEX-A9: Name: .ARM.attributes
-; CORTEX-A9-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; CORTEX-A9-NEXT: Flags [ (0x0)
-; CORTEX-A9-NEXT: ]
-; CORTEX-A9-NEXT: Address: 0x0
-; CORTEX-A9-NEXT: Offset: 0x3C
-; CORTEX-A9-NEXT: Size: 49
-; CORTEX-A9-NEXT: Link: 0
-; CORTEX-A9-NEXT: Info: 0
-; CORTEX-A9-NEXT: AddressAlignment: 1
-; CORTEX-A9-NEXT: EntrySize: 0
-; CORTEX-A9-NEXT: SectionData (
-; CORTEX-A9-NEXT: 0000: 41300000 00616561 62690001 26000000
-; CORTEX-A9-NEXT: 0010: 05434F52 5445582D 41390006 0A074108
-; CORTEX-A9-NEXT: 0020: 0109020A 030C0114 01150117 03180119
-; CORTEX-A9-NEXT: 0030: 01
-; CORTEX-A9-NEXT: )
-
-; CORTEX-A15: Name: .ARM.attributes
-; CORTEX-A15-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; CORTEX-A15-NEXT: Flags [ (0x0)
-; CORTEX-A15-NEXT: ]
-; CORTEX-A15-NEXT: Address: 0x0
-; CORTEX-A15-NEXT: Offset: 0x3C
-; CORTEX-A15-NEXT: Size: 52
-; CORTEX-A15-NEXT: Link: 0
-; CORTEX-A15-NEXT: Info: 0
-; CORTEX-A15-NEXT: AddressAlignment: 1
-; CORTEX-A15-NEXT: EntrySize: 0
-; CORTEX-A15-NEXT: SectionData (
-; CORTEX-A15-NEXT: 0000: 41330000 00616561 62690001 29000000
-; CORTEX-A15-NEXT: 0010: 05434F52 5445582D 41313500 060A0741
-; CORTEX-A15-NEXT: 0020: 08010902 0A050C02 14011501 17031801
-; CORTEX-A15-NEXT: 0030: 19012C02
-; CORTEX-A15-NEXT: )
-
-; CORTEX-M0: Name: .ARM.attributes
-; CORTEX-M0-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; CORTEX-M0-NEXT: Flags [ (0x0)
-; CORTEX-M0-NEXT: ]
-; CORTEX-M0-NEXT: Address: 0x0
-; CORTEX-M0-NEXT: Offset: 0x38
-; CORTEX-M0-NEXT: Size: 45
-; CORTEX-M0-NEXT: Link: 0
-; CORTEX-M0-NEXT: Info: 0
-; CORTEX-M0-NEXT: AddressAlignment: 1
-; CORTEX-M0-NEXT: EntrySize: 0
-; CORTEX-M0-NEXT: SectionData (
-; CORTEX-M0-NEXT: 0000: 412C0000 00616561 62690001 22000000
-; CORTEX-M0-NEXT: 0010: 05434F52 5445582D 4D300006 0C074D08
-; CORTEX-M0-NEXT: 0020: 00090114 01150117 03180119 01
-; CORTEX-M0-NEXT: )
-
-; CORTEX-M4: Name: .ARM.attributes
-; CORTEX-M4-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; CORTEX-M4-NEXT: Flags [ (0x0)
-; CORTEX-M4-NEXT: ]
-; CORTEX-M4-NEXT: Address: 0x0
-; CORTEX-M4-NEXT: Offset: 0x38
-; CORTEX-M4-NEXT: Size: 51
-; CORTEX-M4-NEXT: Link: 0
-; CORTEX-M4-NEXT: Info: 0
-; CORTEX-M4-NEXT: AddressAlignment: 1
-; CORTEX-M4-NEXT: EntrySize: 0
-; CORTEX-M4-NEXT: SectionData (
-; CORTEX-M4-NEXT: 0000: 41320000 00616561 62690001 28000000
-; CORTEX-M4-NEXT: 0010: 05434F52 5445582D 4D340006 0D074D08
-; CORTEX-M4-NEXT: 0020: 0009020A 06140115 01170318 0119011B
-; CORTEX-M4-NEXT: 0030: 012C00
-; CORTEX-M4-NEXT: )
-
-; CORTEX-R5: Name: .ARM.attributes
-; CORTEX-R5-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
-; CORTEX-R5-NEXT: Flags [ (0x0)
-; CORTEX-R5-NEXT: ]
-; CORTEX-R5-NEXT: Address: 0x0
-; CORTEX-R5-NEXT: Offset: 0x3C
-; CORTEX-R5-NEXT: Size: 51
-; CORTEX-R5-NEXT: Link: 0
-; CORTEX-R5-NEXT: Info: 0
-; CORTEX-R5-NEXT: AddressAlignment: 1
-; CORTEX-R5-NEXT: EntrySize: 0
-; CORTEX-R5-NEXT: SectionData (
-; CORTEX-R5-NEXT: 0000: 41320000 00616561 62690001 28000000
-; CORTEX-R5-NEXT: 0010: 05434F52 5445582D 52350006 0A075208
-; CORTEX-R5-NEXT: 0020: 0109020A 04140115 01170318 0119011B
-; CORTEX-R5-NEXT: 0030: 012C02
-; CORTEX-R5-NEXT: )
-
-define i32 @f(i64 %z) {
- ret i32 0
-}
Added: llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s?rev=193859&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s (added)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes-encoding.s Fri Nov 1 08:27:35 2013
@@ -0,0 +1,82 @@
+// This tests that ARM attributes are properly encoded.
+
+// RUN: llvm-mc < %s -triple=arm-linux-gnueabi -filetype=obj -o - \
+// RUN: | llvm-readobj -s -sd | FileCheck %s
+
+// Tag_CPU_name (=5)
+.cpu Cortex-A8
+
+// Tag_CPU_arch (=6)
+.eabi_attribute 6, 10
+
+// Tag_arch_profile (=7)
+.eabi_attribute 7, 'A'
+
+// Tag_ARM_ISA_use (=8)
+.eabi_attribute 8, 1
+
+// Tag_THUMB_ISA_use (=9)
+.eabi_attribute 9, 2
+
+// Tag_FP_arch (=10)
+.fpu vfpv3
+
+// Tag_Advanced_SIMD_arch (=12)
+.eabi_attribute 12, 2
+
+// Tag_ABI_FP_denormal (=20)
+.eabi_attribute 20, 1
+
+// Tag_ABI_FP_exceptions (=21)
+.eabi_attribute 21, 1
+
+// Tag_ABI_FP_number_model (=23)
+.eabi_attribute 23, 1
+
+// Tag_ABI_align_needed (=24)
+.eabi_attribute 24, 1
+
+// Tag_ABI_align_preserved (=25)
+.eabi_attribute 25, 1
+
+// Tag_ABI_HardFP_use (=27)
+.eabi_attribute 27, 0
+
+// Tag_ABI_VFP_args (=28)
+.eabi_attribute 28, 1
+
+// Tag_MPextension_use (=42)
+.eabi_attribute 42, 1
+
+// Tag_DIV_use (=44)
+.eabi_attribute 44, 2
+
+// Tag_Virtualization_use (=68)
+.eabi_attribute 68, 3
+
+// Check that values > 128 are encoded properly
+.eabi_attribute 110, 160
+
+// Check that tags > 128 are encoded properly
+.eabi_attribute 129, 1
+.eabi_attribute 250, 1
+
+// CHECK: Section {
+// CHECK: Name: .ARM.attributes
+// CHECK-NEXT: Type: SHT_ARM_ATTRIBUTES
+// CHECK-NEXT: Flags [ (0x0)
+// CHECK-NEXT: ]
+// CHECK-NEXT: Address: 0x0
+// CHECK-NEXT: Offset: 0x34
+// CHECK-NEXT: Size: 68
+// CHECK-NEXT: Link: 0
+// CHECK-NEXT: Info: 0
+// CHECK-NEXT: AddressAlignment: 1
+// CHECK-NEXT: EntrySize: 0
+// CHECK-NEXT: SectionData (
+// CHECK-NEXT: 0000: 41430000 00616561 62690001 39000000
+// CHECK-NEXT: 0010: 05434F52 5445582D 41380006 0A074108
+// CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119
+// CHECK-NEXT: 0030: 011B001C 012A012C 0244036E A0018101
+// CHECK-NEXT: 0040: 01FA0101
+// CHECK-NEXT: )
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