[llvm] r193816 - [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
Chad Rosier
mcrosier at codeaurora.org
Thu Oct 31 15:37:00 PDT 2013
Author: mcrosier
Date: Thu Oct 31 17:36:59 2013
New Revision: 193816
URL: http://llvm.org/viewvc/llvm-project?rev=193816&view=rev
Log:
[AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
llvm/trunk/test/CodeGen/AArch64/neon-scalar-cvt.ll
llvm/trunk/test/MC/AArch64/neon-diagnostics.s
llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s
llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
Modified: llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td?rev=193816&r1=193815&r2=193816&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td Thu Oct 31 17:36:59 2013
@@ -260,4 +260,15 @@ def int_aarch64_neon_vsrid_n : Neon_2Arg
// Shift Left And Insert (Immediate)
def int_aarch64_neon_vslid_n : Neon_2Arg_ShiftImm_Intrinsic;
+// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
+def int_aarch64_neon_vcvtf32_n_s32 :
+ Intrinsic<[llvm_v1f32_ty], [llvm_v1i32_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_aarch64_neon_vcvtf64_n_s64 :
+ Intrinsic<[llvm_v1f64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
+
+// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
+def int_aarch64_neon_vcvtf32_n_u32 :
+ Intrinsic<[llvm_v1f32_ty], [llvm_v1i32_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_aarch64_neon_vcvtf64_n_u64 :
+ Intrinsic<[llvm_v1f64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td?rev=193816&r1=193815&r2=193816&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td Thu Oct 31 17:36:59 2013
@@ -3607,6 +3607,19 @@ multiclass NeonI_ScalarShiftImm_narrow_H
}
}
+multiclass NeonI_ScalarShiftImm_scvtf_SD_size<bit u, bits<5> opcode, string asmop> {
+ def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
+ bits<5> Imm;
+ let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
+ let Inst{20-16} = Imm;
+ }
+ def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
+ bits<6> Imm;
+ let Inst{22} = 0b1; // immh:immb = 1xxxxxx
+ let Inst{21-16} = Imm;
+ }
+}
+
multiclass Neon_ScalarShiftImm_D_size_patterns<SDPatternOperator opnode,
Instruction INSTD> {
def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
@@ -3645,6 +3658,16 @@ multiclass Neon_ScalarShiftImm_narrow_HS
(INSTD FPR64:$Rn, imm:$Imm)>;
}
+multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
+ SDPatternOperator Dopnode,
+ Instruction INSTS,
+ Instruction INSTD> {
+ def ssi : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
+ (INSTS FPR32:$Rn, imm:$Imm)>;
+ def ddi : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
+ (INSTD FPR64:$Rn, imm:$Imm)>;
+}
+
// Scalar Signed Shift Right (Immediate)
defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
@@ -3743,6 +3766,18 @@ defm : Neon_ScalarShiftImm_narrow_HSD_si
SQRSHRUNbhi, SQRSHRUNhsi,
SQRSHRUNsdi>;
+// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
+defm SCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b0, 0b11100, "scvtf">;
+defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
+ int_aarch64_neon_vcvtf64_n_s64,
+ SCVTF_Nssi, SCVTF_Nddi>;
+
+// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
+defm UCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b1, 0b11100, "ucvtf">;
+defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
+ int_aarch64_neon_vcvtf64_n_u64,
+ UCVTF_Nssi, UCVTF_Nddi>;
+
// Scalar Integer Add
let isCommutable = 1 in {
def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
Modified: llvm/trunk/test/CodeGen/AArch64/neon-scalar-cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-scalar-cvt.ll?rev=193816&r1=193815&r2=193816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-scalar-cvt.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-scalar-cvt.ll Thu Oct 31 17:36:59 2013
@@ -47,3 +47,51 @@ entry:
}
declare <1 x double> @llvm.aarch64.neon.vcvtf64.u64(<1 x i64>)
+
+define float @test_vcvts_n_f32_s32(i32 %a) {
+; CHECK: test_vcvts_n_f32_s32
+; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
+entry:
+ %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
+ %vcvtf1 = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1)
+ %0 = extractelement <1 x float> %vcvtf1, i32 0
+ ret float %0
+}
+
+declare <1 x float> @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32>, i32)
+
+define double @test_vcvtd_n_f64_s64(i64 %a) {
+; CHECK: test_vcvtd_n_f64_s64
+; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
+entry:
+ %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
+ %vcvtf1 = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1)
+ %0 = extractelement <1 x double> %vcvtf1, i32 0
+ ret double %0
+}
+
+declare <1 x double> @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64>, i32)
+
+define float @test_vcvts_n_f32_u32(i32 %a) {
+; CHECK: test_vcvts_n_f32_u32
+; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
+entry:
+ %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
+ %vcvtf1 = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1)
+ %0 = extractelement <1 x float> %vcvtf1, i32 0
+ ret float %0
+}
+
+declare <1 x float> @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32>, i32)
+
+define double @test_vcvtd_n_f64_u64(i64 %a) {
+; CHECK: test_vcvtd_n_f64_u64
+; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
+entry:
+ %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
+ %vcvtf1 = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1)
+ %0 = extractelement <1 x double> %vcvtf1, i32 0
+ ret double %0
+}
+
+declare <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64>, i32)
Modified: llvm/trunk/test/MC/AArch64/neon-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=193816&r1=193815&r2=193816&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-diagnostics.s Thu Oct 31 17:36:59 2013
@@ -4992,3 +4992,43 @@
// CHECK-ERROR: error: expected integer in range [1, 32]
// CHECK-ERROR: sqrshrun s22, d16, #99
// CHECK-ERROR: ^
+
+//----------------------------------------------------------------------
+// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
+//----------------------------------------------------------------------
+
+ scvtf s22, s13, #0
+ scvtf s22, s13, #33
+ scvtf d21, d12, #65
+ scvtf d21, s12, #31
+
+// CHECK-ERROR: error: expected integer in range [1, 32]
+// CHECK-ERROR: scvtf s22, s13, #0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: expected integer in range [1, 32]
+// CHECK-ERROR: scvtf s22, s13, #33
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: expected integer in range [1, 64]
+// CHECK-ERROR: scvtf d21, d12, #65
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: scvtf d21, s12, #31
+// CHECK-ERROR: ^
+
+//----------------------------------------------------------------------
+// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
+//----------------------------------------------------------------------
+
+ ucvtf s22, s13, #34
+ ucvtf d21, d14, #65
+ ucvtf d21, s14, #64
+
+// CHECK-ERROR: error: expected integer in range [1, 32]
+// CHECK-ERROR: ucvtf s22, s13, #34
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: expected integer in range [1, 64]
+// CHECK-ERROR: ucvtf d21, d14, #65
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: ucvtf d21, s14, #64
+// CHECK-ERROR: ^
Modified: llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s?rev=193816&r1=193815&r2=193816&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-scalar-cvt.s Thu Oct 31 17:36:59 2013
@@ -21,3 +21,23 @@
// CHECK: ucvtf s22, s13 // encoding: [0xb6,0xd9,0x21,0x7e]
// CHECK: ucvtf d21, d14 // encoding: [0xd5,0xd9,0x61,0x7e]
+
+//----------------------------------------------------------------------
+// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
+//----------------------------------------------------------------------
+
+ scvtf s22, s13, #32
+ scvtf d21, d12, #64
+
+// CHECK: scvtf s22, s13, #32 // encoding: [0xb6,0xe5,0x20,0x5f]
+// CHECK: scvtf d21, d12, #64 // encoding: [0x95,0xe5,0x40,0x5f]
+
+//----------------------------------------------------------------------
+// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
+//----------------------------------------------------------------------
+
+ ucvtf s22, s13, #32
+ ucvtf d21, d14, #64
+
+// CHECK: ucvtf s22, s13, #32 // encoding: [0xb6,0xe5,0x20,0x7f]
+// CHECK: ucvtf d21, d14, #64 // encoding: [0xd5,0xe5,0x40,0x7f]
Modified: llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt?rev=193816&r1=193815&r2=193816&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/neon-instructions.txt Thu Oct 31 17:36:59 2013
@@ -1955,3 +1955,19 @@
0x51,0x8d,0x0a,0x7f
0xaa,0x8d,0x11,0x7f
0x16,0x8e,0x21,0x7f
+
+#----------------------------------------------------------------------
+# Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
+#----------------------------------------------------------------------
+# CHECK: scvtf s22, s13, #32
+# CHECK: scvtf d21, d12, #64
+0xb6,0xe5,0x20,0x5f
+0x95,0xe5,0x40,0x5f
+
+#----------------------------------------------------------------------
+# Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
+#----------------------------------------------------------------------
+# CHECK: ucvtf s22, s13, #32
+# CHECK: ucvtf d21, d14, #64
+0xb6,0xe5,0x20,0x7f
+0xd5,0xe5,0x40,0x7f
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