[llvm] r193789 - SparcV9 doesnt have rem instruction either.

[Roman Divacky]

Author: rdivacky
Date: Thu Oct 31 14:22:33 2013
New Revision: 193789

URL: http://llvm.org/viewvc/llvm-project?rev=193789&view=rev
Log:
SparcV9 doesnt have rem instruction either.

Added:
    llvm/trunk/test/CodeGen/SPARC/rem.ll
Modified:
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=193789&r1=193788&r2=193789&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Thu Oct 31 14:22:33 2013
@@ -1341,6 +1341,14 @@ SparcTargetLowering::SparcTargetLowering
   setOperationAction(ISD::SREM, MVT::i32, Expand);
   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+  
+  // ... nor does SparcV9.
+  if (Subtarget->is64Bit()) {
+    setOperationAction(ISD::UREM, MVT::i64, Expand);
+    setOperationAction(ISD::SREM, MVT::i64, Expand);
+    setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
+    setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
+  }
 
   // Custom expand fp<->sint
   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);

Added: llvm/trunk/test/CodeGen/SPARC/rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/rem.ll?rev=193789&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/rem.ll (added)
+++ llvm/trunk/test/CodeGen/SPARC/rem.ll Thu Oct 31 14:22:33 2013
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=sparcv9 | FileCheck %s
+
+; CHECK-LABEL: test1:
+; CHECK:        sdivx %o0, %o1, %o2
+; CHECK-NEXT:   mulx %o2, %o1, %o1
+; CHECK-NEXT:   jmp %o7+8
+; CHECK-NEXT:   sub %o0, %o1, %o0
+
+define i64 @test1(i64 %X, i64 %Y) {
+        %tmp1 = srem i64 %X, %Y
+        ret i64 %tmp1
+}
+
+; CHECK-LABEL: test2:
+; CHECK:        udivx %o0, %o1, %o2
+; CHECK-NEXT:   mulx %o2, %o1, %o1
+; CHECK-NEXT:   jmp %o7+8
+; CHECK-NEXT:   sub %o0, %o1, %o0
+
+define i64 @test2(i64 %X, i64 %Y) {
+        %tmp1 = urem i64 %X, %Y
+        ret i64 %tmp1
+}