[PATCH] [AArch64] Make FP instructions optional

[Amara Emerson]

  Following the discussion with Bernie, we've decided to make NEON imply FP, which should simplify things a bit.

  I've made load/stores to the FP registers predicated on FP, so instructions like ldr s0, [x0] are now disallowed.

  Also cleaned up the tests, the previous superfluous +fp-armv8s were left over after I made FP enabled by default but didn't update the tests. Some tests were merged together as you suggested.

Hi t.p.northover,

http://llvm-reviews.chandlerc.com/D2052

CHANGE SINCE LAST DIFF
  http://llvm-reviews.chandlerc.com/D2052?vs=5223&id=5262#toc

Files:
  lib/Target/AArch64/AArch64.td
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64Subtarget.cpp
  lib/Target/AArch64/AArch64Subtarget.h
  test/CodeGen/AArch64/alloca.ll
  test/CodeGen/AArch64/cond-sel.ll
  test/CodeGen/AArch64/directcond.ll
  test/CodeGen/AArch64/func-argpassing.ll
  test/CodeGen/AArch64/func-calls.ll
  test/CodeGen/AArch64/ldst-regoffset.ll
  test/CodeGen/AArch64/ldst-unscaledimm.ll
  test/CodeGen/AArch64/ldst-unsignedimm.ll
  test/CodeGen/AArch64/literal_pools.ll
  test/CodeGen/AArch64/variadic.ll
  test/MC/AArch64/basic-a64-instructions.s
  test/MC/AArch64/elf-reloc-ldstunsimm.s
  test/MC/AArch64/inline-asm-modifiers.s
  test/MC/Disassembler/AArch64/a64-ignored-fields.txt
  test/MC/Disassembler/AArch64/basic-a64-instructions.txt
  test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt
  test/MC/Disassembler/AArch64/ldp-postind.predictable.txt
  test/MC/Disassembler/AArch64/ldp-preind.predictable.txt
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D2052.2.patch
Type: text/x-patch
Size: 38021 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20131030/5c62eb20/attachment.bin>