[llvm] r193677 - Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."
Juergen Ributzka
juergen at apple.com
Tue Oct 29 23:36:19 PDT 2013
Author: ributzka
Date: Wed Oct 30 01:36:19 2013
New Revision: 193677
URL: http://llvm.org/viewvc/llvm-project?rev=193677&view=rev
Log:
Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."
Now Hexagon and SystemZ are not happy with it :-(
Removed:
llvm/trunk/test/CodeGen/X86/vec_split.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=193677&r1=193676&r2=193677&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Oct 30 01:36:19 2013
@@ -4346,28 +4346,6 @@ SDValue DAGCombiner::visitVSELECT(SDNode
}
}
- // Treat SETCC as a vector mask and promote the result type based on the
- // targets expected SETCC result type. This will ensure that SETCC and VSELECT
- // are both split by the type legalizer. This is done to prevent the type
- // legalizer from unrolling SETCC into scalar comparions.
- EVT SelectVT = N->getValueType(0);
- EVT MaskVT = getSetCCResultType(SelectVT);
- if (N0.getOpcode() == ISD::SETCC && N0.getValueType() != MaskVT) {
- SDLoc MaskDL(N0);
-
- // Extend the mask to the desired value type.
- ISD::NodeType ExtendCode =
- TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
- SDValue Mask = DAG.getNode(ExtendCode, MaskDL, MaskVT, N0);
-
- AddToWorkList(Mask.getNode());
-
- SDValue LHS = N->getOperand(1);
- SDValue RHS = N->getOperand(2);
-
- return DAG.getNode(ISD::VSELECT, DL, SelectVT, Mask, LHS, RHS);
- }
-
return SDValue();
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=193677&r1=193676&r2=193677&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Wed Oct 30 01:36:19 2013
@@ -492,19 +492,14 @@ void DAGTypeLegalizer::SplitRes_SELECT(S
SDValue Cond = N->getOperand(0);
CL = CH = Cond;
if (Cond.getValueType().isVector()) {
- if (Cond.getOpcode() == ISD::SETCC) {
- assert(Cond.getValueType() == getSetCCResultType(N->getValueType(0)) &&
- "Condition has not been prepared for split!");
- GetSplitVector(Cond, CL, CH);
- } else {
- EVT ETy = Cond.getValueType().getVectorElementType();
- unsigned NumElements = Cond.getValueType().getVectorNumElements();
- EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), ETy, NumElements / 2);
- CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
- DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
- }
+ assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
+ "Condition legalized before result?");
+ unsigned NumElements = Cond.getValueType().getVectorNumElements();
+ EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
+ CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
+ DAG.getConstant(0, TLI.getVectorIdxTy()));
+ CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
+ DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
}
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=193677&r1=193676&r2=193677&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Oct 30 01:36:19 2013
@@ -1546,16 +1546,7 @@ void X86TargetLowering::resetOperationAc
}
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
- if (!VT.isVector())
- return MVT::i8;
-
- const TargetMachine &TM = getTargetMachine();
- if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
- switch(VT.getVectorNumElements()) {
- case 8: return MVT::v8i1;
- case 16: return MVT::v16i1;
- }
-
+ if (!VT.isVector()) return MVT::i8;
return VT.changeVectorElementTypeToInteger();
}
Removed: llvm/trunk/test/CodeGen/X86/vec_split.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_split.ll?rev=193676&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_split.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_split.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4
-; RUN: llc -march=x86-64 -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1
-; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
-
-define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) {
-; SSE4-LABEL: split16:
-; SSE4: pminuw
-; SSE4: pminuw
-; SSE4: ret
-; AVX1-LABEL: split16:
-; AVX1: vpminuw
-; AVX1: vpminuw
-; AVX1: ret
-; AVX2-LABEL: split16:
-; AVX2: vpminuw
-; AVX2: ret
- %1 = icmp ult <16 x i16> %a, %b
- %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
- ret <16 x i16> %2
-}
-
-define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) {
-; SSE4-LABEL: split32:
-; SSE4: pminuw
-; SSE4: pminuw
-; SSE4: pminuw
-; SSE4: pminuw
-; SSE4: ret
-; AVX1-LABEL: split32:
-; AVX1: vpminuw
-; AVX1: vpminuw
-; AVX1: vpminuw
-; AVX1: vpminuw
-; AVX1: ret
-; AVX2-LABEL: split32:
-; AVX2: vpminuw
-; AVX2: vpminuw
-; AVX2: ret
- %1 = icmp ult <32 x i16> %a, %b
- %2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b
- ret <32 x i16> %2
-}
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