[llvm] r193673 - [mips] Compute stack alignment on the fly.

[Akira Hatanaka]

Author: ahatanak
Date: Tue Oct 29 21:29:43 2013
New Revision: 193673

URL: http://llvm.org/viewvc/llvm-project?rev=193673&view=rev
Log:
[mips] Compute stack alignment on the fly.

Modified:
    llvm/trunk/lib/Target/Mips/Mips.td
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h

Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=193673&r1=193672&r2=193673&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Tue Oct 29 21:29:43 2013
@@ -30,12 +30,10 @@ def MipsInstrInfo : InstrInfo;
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
-def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
-                                    "Set stack alignment to 16-bytes.">;
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
-                                "Support 64-bit FP registers.", [StackAlign16]>;
+                                "Support 64-bit FP registers.">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=193673&r1=193672&r2=193673&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Oct 29 21:29:43 2013
@@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::
   InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
   InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
   AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-  StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
+  RM(_RM), OverrideMode(NoOverride), TM(_TM)
 {
   std::string CPUName = CPU;
   if (CPUName.empty())

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=193673&r1=193672&r2=193673&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Oct 29 21:29:43 2013
@@ -116,8 +116,6 @@ protected:
   // HasMSA -- supports MSA ASE.
   bool HasMSA;
 
-  unsigned StackAlignment;
-
   InstrItineraryData InstrItins;
 
   // The instance to the register info section object
@@ -219,7 +217,7 @@ public:
 //
 static bool useConstantIslands();
 
-  unsigned stackAlignment() const { return StackAlignment; }
+  unsigned stackAlignment() const { return isFP64bit() ? 16 : 8; }
 
   // Grab MipsRegInfo object
   const MipsReginfo &getMReginfo() const { return MRI; }