[llvm] r193641 - [mips] Align the stack to 16-bytes for mfp64.
Akira Hatanaka
ahatanaka at mips.com
Tue Oct 29 12:29:04 PDT 2013
Author: ahatanak
Date: Tue Oct 29 14:29:03 2013
New Revision: 193641
URL: http://llvm.org/viewvc/llvm-project?rev=193641&view=rev
Log:
[mips] Align the stack to 16-bytes for mfp64.
Added:
llvm/trunk/test/CodeGen/Mips/stack-alignment.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/Mips16FrameLowering.h
llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.h
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=193641&r1=193640&r2=193641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Tue Oct 29 14:29:03 2013
@@ -30,10 +30,12 @@ def MipsInstrInfo : InstrInfo;
// Mips Subtarget features //
//===----------------------------------------------------------------------===//
+def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
+ "Set stack alignment to 16-bytes.">;
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
- "Support 64-bit FP registers.">;
+ "Support 64-bit FP registers.", [StackAlign16]>;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">;
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
Modified: llvm/trunk/lib/Target/Mips/Mips16FrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16FrameLowering.h?rev=193641&r1=193640&r2=193641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16FrameLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips16FrameLowering.h Tue Oct 29 14:29:03 2013
@@ -20,7 +20,7 @@ namespace llvm {
class Mips16FrameLowering : public MipsFrameLowering {
public:
explicit Mips16FrameLowering(const MipsSubtarget &STI)
- : MipsFrameLowering(STI, 8) {}
+ : MipsFrameLowering(STI, STI.stackAlignment()) {}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.h?rev=193641&r1=193640&r2=193641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.h Tue Oct 29 14:29:03 2013
@@ -21,7 +21,7 @@ namespace llvm {
class MipsSEFrameLowering : public MipsFrameLowering {
public:
explicit MipsSEFrameLowering(const MipsSubtarget &STI)
- : MipsFrameLowering(STI, STI.hasMips64() ? 16 : 8) {}
+ : MipsFrameLowering(STI, STI.stackAlignment()) {}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=193641&r1=193640&r2=193641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Oct 29 14:29:03 2013
@@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
- RM(_RM), OverrideMode(NoOverride), TM(_TM)
+ StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
{
std::string CPUName = CPU;
if (CPUName.empty())
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=193641&r1=193640&r2=193641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Oct 29 14:29:03 2013
@@ -116,6 +116,8 @@ protected:
// HasMSA -- supports MSA ASE.
bool HasMSA;
+ unsigned StackAlignment;
+
InstrItineraryData InstrItins;
// The instance to the register info section object
@@ -216,6 +218,9 @@ public:
// really use them if in addition we are in mips16 mode
//
static bool useConstantIslands();
+
+ unsigned stackAlignment() const { return StackAlignment; }
+
// Grab MipsRegInfo object
const MipsReginfo &getMReginfo() const { return MRI; }
Added: llvm/trunk/test/CodeGen/Mips/stack-alignment.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/stack-alignment.ll?rev=193641&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/stack-alignment.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/stack-alignment.ll Tue Oct 29 14:29:03 2013
@@ -0,0 +1,14 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32-FP64
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+
+; 32: addiu $sp, $sp, -8
+; 32-FP64: addiu $sp, $sp, -16
+; 64: addiu $sp, $sp, -16
+
+define i32 @foo1() #0 {
+entry:
+ ret i32 14
+}
+
+attributes #0 = { "no-frame-pointer-elim"="true" }
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