[llvm] r193599 - ARM: Add subtarget feature for CRC
Bradley Smith
bradley.smith at arm.com
Tue Oct 29 09:12:46 PDT 2013
Hi,
I believe this patch has left HasCRC potentially uninitialized for cores
without the feature explicitly enabled, (i.e. the variable is not set in
ARMSubtarget::initializeEnvironment).
Regards,
Bradley Smith
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Bernard Ogden
> Sent: 29 October 2013 09:48
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r193599 - ARM: Add subtarget feature for CRC
>
> Author: bogden
> Date: Tue Oct 29 04:47:35 2013
> New Revision: 193599
>
> URL: http://llvm.org/viewvc/llvm-project?rev=193599&view=rev
> Log:
> ARM: Add subtarget feature for CRC
>
> Adds a subtarget feature for the CRC instructions (optional in v8-A) to
> the ARM (32-bit) backend.
>
> Differential Revision: http://llvm-reviews.chandlerc.com/D2036
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARM.td
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> llvm/trunk/test/MC/ARM/crc32-thumb.s
> llvm/trunk/test/MC/ARM/crc32.s
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.td
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARM.td?rev=193599&r1=193598&r2=193599
> &view=diff
> =======================================================================
> =======
> --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.td Tue Oct 29 04:47:35 2013
> @@ -70,6 +70,8 @@ def FeatureTrustZone : SubtargetFeature<
> def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
> "Enable support for Cryptography
> extensions",
> [FeatureNEON]>;
> +def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
> + "Enable support for CRC instructions">;
>
> // Some processors have FP multiply-accumulate instructions that don't
> // play nicely with other VFP / NEON instructions, and it's generally
> better
> @@ -202,13 +204,13 @@ def ProcA53 : SubtargetFeature<"a53"
> "Cortex-A53 ARM processors",
> [FeatureMP, FeatureHWDiv,
> FeatureHWDivARM,
> FeatureTrustZone, FeatureT2XtPk,
> - FeatureCrypto]>;
> + FeatureCrypto, FeatureCRC]>;
>
> def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily",
> "CortexA57",
> "Cortex-A57 ARM processors",
> [FeatureMP, FeatureHWDiv,
> FeatureHWDivARM,
> FeatureTrustZone, FeatureT2XtPk,
> - FeatureCrypto]>;
> + FeatureCrypto, FeatureCRC]>;
>
> def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
> "Cortex-R5 ARM processors",
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=193599&r1=193598&
> r2=193599&view=diff
> =======================================================================
> =======
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 29 04:47:35 2013
> @@ -221,6 +221,8 @@ def HasNEON : Predicate<"Subtar
> AssemblerPredicate<"FeatureNEON",
> "NEON">;
> def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
> AssemblerPredicate<"FeatureCrypto",
> "crypto">;
> +def HasCRC : Predicate<"Subtarget->hasCRC()">,
> + AssemblerPredicate<"FeatureCRC",
> "crc">;
> def HasFP16 : Predicate<"Subtarget->hasFP16()">,
>
> AssemblerPredicate<"FeatureFP16","half-float">;
> def HasDivide : Predicate<"Subtarget->hasDivide()">,
> @@ -4032,7 +4034,7 @@ class AI_crc32<bit C, bits<2> sz, string
> : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm,
> NoItinerary,
> !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
> [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn,
> GPRnopc:$Rm))]>,
> - Requires<[IsARM, HasV8]> {
> + Requires<[IsARM, HasV8, HasCRC]> {
> bits<4> Rd;
> bits<4> Rn;
> bits<4> Rm;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=193599&r1=19359
> 8&r2=193599&view=diff
> =======================================================================
> =======
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Oct 29 04:47:35
> 2013
> @@ -3027,7 +3027,7 @@ class T2I_crc32<bit C, bits<2> sz, strin
> : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
> NoItinerary,
> !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
> [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
> - Requires<[IsThumb2, HasV8]> {
> + Requires<[IsThumb2, HasV8, HasCRC]> {
> let Inst{31-27} = 0b11111;
> let Inst{26-21} = 0b010110;
> let Inst{20} = C;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=193599&r1=193598&r
> 2=193599&view=diff
> =======================================================================
> =======
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Oct 29 04:47:35 2013
> @@ -165,6 +165,9 @@ protected:
> /// HasCrypto - if true, processor supports Cryptography extensions
> bool HasCrypto;
>
> + /// HasCRC - if true, processor supports CRC instructions
> + bool HasCRC;
> +
> /// AllowsUnalignedMem - If true, the subtarget allows unaligned
> memory
> /// accesses for some types. For details, see
> /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
> @@ -256,6 +259,7 @@ public:
> bool hasFPARMv8() const { return HasFPARMv8; }
> bool hasNEON() const { return HasNEON; }
> bool hasCrypto() const { return HasCrypto; }
> + bool hasCRC() const { return HasCRC; }
> bool useNEONForSinglePrecisionFP() const {
> return hasNEON() && UseNEONForSinglePrecisionFP; }
>
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=
> 193599&r1=193598&r2=193599&view=diff
> =======================================================================
> =======
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Tue Oct
> 29 04:47:35 2013
> @@ -105,8 +105,8 @@ std::string ARM_MC::ParseARMTriple(Strin
> if (SubVer == '8') {
> if (NoCPU)
> // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON,
> FeatureDSPThumb2, FeatureMP,
> - // FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
> FeatureT2XtPk, FeatureCrypto
> - ARMArchFeature = "+v8,+db,+fp-
> armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto";
> + // FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
> FeatureT2XtPk, FeatureCrypto, FeatureCRC
> + ARMArchFeature = "+v8,+db,+fp-
> armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-
> arm,+trustzone,+t2xtpk,+crypto,+crc";
> else
> // Use CPU to figure out the exact features
> ARMArchFeature = "+v8";
>
> Modified: llvm/trunk/test/MC/ARM/crc32-thumb.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/crc32-
> thumb.s?rev=193599&r1=193598&r2=193599&view=diff
> =======================================================================
> =======
> --- llvm/trunk/test/MC/ARM/crc32-thumb.s (original)
> +++ llvm/trunk/test/MC/ARM/crc32-thumb.s Tue Oct 29 04:47:35 2013
> @@ -1,5 +1,6 @@
> @ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
> @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 |
> FileCheck %s --check-prefix=CHECK-V7
> +@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s
> 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
> crc32b r0, r1, r2
> crc32h r0, r1, r2
> crc32w r0, r1, r2
> @@ -7,9 +8,12 @@
> @ CHECK: crc32b r0, r1, r2 @ encoding:
> [0xc1,0xfa,0x82,0xf0]
> @ CHECK: crc32h r0, r1, r2 @ encoding:
> [0xc1,0xfa,0x92,0xf0]
> @ CHECK: crc32w r0, r1, r2 @ encoding:
> [0xc1,0xfa,0xa2,0xf0]
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
>
> crc32cb r0, r1, r2
> crc32ch r0, r1, r2
> @@ -18,6 +22,9 @@
> @ CHECK: crc32cb r0, r1, r2 @ encoding:
> [0xd1,0xfa,0x82,0xf0]
> @ CHECK: crc32ch r0, r1, r2 @ encoding:
> [0xd1,0xfa,0x92,0xf0]
> @ CHECK: crc32cw r0, r1, r2 @ encoding:
> [0xd1,0xfa,0xa2,0xf0]
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
>
> Modified: llvm/trunk/test/MC/ARM/crc32.s
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/MC/ARM/crc32.s?rev=193599&r1=193598&r2=193599&v
> iew=diff
> =======================================================================
> =======
> --- llvm/trunk/test/MC/ARM/crc32.s (original)
> +++ llvm/trunk/test/MC/ARM/crc32.s Tue Oct 29 04:47:35 2013
> @@ -1,5 +1,6 @@
> @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
> @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck
> %s --check-prefix=CHECK-V7
> +@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s
> 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
> crc32b r0, r1, r2
> crc32h r0, r1, r2
> crc32w r0, r1, r2
> @@ -7,9 +8,12 @@
> @ CHECK: crc32b r0, r1, r2 @ encoding:
> [0x42,0x00,0x01,0xe1]
> @ CHECK: crc32h r0, r1, r2 @ encoding:
> [0x42,0x00,0x21,0xe1]
> @ CHECK: crc32w r0, r1, r2 @ encoding:
> [0x42,0x00,0x41,0xe1]
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
>
> crc32cb r0, r1, r2
> crc32ch r0, r1, r2
> @@ -18,6 +22,9 @@
> @ CHECK: crc32cb r0, r1, r2 @ encoding:
> [0x42,0x02,0x01,0xe1]
> @ CHECK: crc32ch r0, r1, r2 @ encoding:
> [0x42,0x02,0x21,0xe1]
> @ CHECK: crc32cw r0, r1, r2 @ encoding:
> [0x42,0x02,0x41,0xe1]
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> -@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-V7: error: instruction requires: crc armv8
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
> +@ CHECK-NOCRC: error: instruction requires: crc
>
>
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