[PATCH] R600/SI: Display neg/abs operand the same way as R600

[Tom Stellard]

On Mon, Oct 21, 2013 at 09:36:05PM -0700, Owen Anderson wrote:
> 
> On Oct 21, 2013, at 12:29 PM, Tom Stellard <tom at stellard.net> wrote:
> 
> > On Mon, Oct 21, 2013 at 03:03:46PM +0200, Vincent Lejeune wrote:
> >> ---
> >> lib/Target/R600/AMDGPUInstructions.td |  9 +++++-
> >> lib/Target/R600/R600Instructions.td   |  7 -----
> >> lib/Target/R600/SIISelLowering.cpp    | 45 +++++++++++++++++++++++---
> >> lib/Target/R600/SIInstrFormats.td     | 24 ++++++++++----
> >> lib/Target/R600/SIInstrInfo.td        | 59 ++++++++++++++++++++++++-----------
> >> lib/Target/R600/SIInstructions.td     | 24 ++++++--------
> >> test/CodeGen/R600/fabs.ll             |  2 +-
> >> test/CodeGen/R600/fneg.ll             | 23 ++++++++------
> >> test/CodeGen/R600/fsub64.ll           |  2 +-
> >> test/CodeGen/R600/seto.ll             |  2 +-
> >> test/CodeGen/R600/setuo.ll            |  2 +-
> >> 11 files changed, 136 insertions(+), 63 deletions(-)
> >> 
> > 
> > I'm not a huge fan of adding all these extra operands, but I'm not sure
> > there is a better way to get the assembly output we want.
> 
> You could consider batching them up.  For instance, all the modifiers to operand 1 could be bits in a single immediate operand.  This ends up looking like the ComplexPattern's that most targets use for addressing modes.
>

This would work except that the abs modifier needs to be printed before
and after the operand, but the negate modifier only needs to be printed
before.  For example, we want to print the abs modifier like this:

|VGPR0|

and this requires defining an assembly string in tablegen like this:

$src0_abs$src0$src0_abs

If we merged them all together and did something like:

$src0_mod$src0$src0_mod, we would end up with negated operands that look
like this:

-VGPR0-

I know next to nothing about the assembly printer, so maybe there is a
more elegant way to implement this, but I'm not sure what it is.

-Tom