[PATCH] [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen

[Amara Emerson]

Ping. Any comments on this patch Tim?

Cheers,
Amara


On 16 October 2013 13:53, Amara Emerson <amara.emerson at arm.com> wrote:

> Hi t.p.northover,
>
> When generating the IfTrue basic block during the F128CSEL
> pseudo-instruction handling, the NZCV live-in for the newly created BB
> wasn't being added. This caused a fault during MI-sched/live range
> calculation when the predecessor for the fall-through BB didn't have a
> live-in for phys-reg as expected.
>
> Review appreciated.
>
> http://llvm-reviews.chandlerc.com/D1949
>
> Files:
>   lib/Target/AArch64/AArch64ISelLowering.cpp
>   test/CodeGen/AArch64/fp128-livein.ll
>
> Index: lib/Target/AArch64/AArch64ISelLowering.cpp
> ===================================================================
> --- lib/Target/AArch64/AArch64ISelLowering.cpp
> +++ lib/Target/AArch64/AArch64ISelLowering.cpp
> @@ -699,6 +699,12 @@
>    MBB->addSuccessor(TrueBB);
>    MBB->addSuccessor(EndBB);
>
> +  if (!NZCVKilled) {
> +    // NZCV is live-through TrueBB.
> +    TrueBB->addLiveIn(AArch64::NZCV);
> +    EndBB->addLiveIn(AArch64::NZCV);
> +  }
> +
>    // IfTrue:
>    //     str qIFTRUE, [sp]
>    BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
> @@ -713,8 +719,6 @@
>    // Done:
>    //     ldr qDEST, [sp]
>    //     [... rest of incoming MBB ...]
> -  if (!NZCVKilled)
> -    EndBB->addLiveIn(AArch64::NZCV);
>    MachineInstr *StartOfEnd = EndBB->begin();
>    BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
>      .addFrameIndex(ScratchFI)
> Index: test/CodeGen/AArch64/fp128-livein.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/AArch64/fp128-livein.ll
> @@ -0,0 +1,17 @@
> +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s
> +
> +; Regression test for NZCV reg live-in not being added to fp128csel
> IfTrue BB,
> +; causing a crash during live range calc.
> +define void @fp128_livein(i64 %a) {
> +  %tobool = icmp ne i64 %a, 0
> +  %conv = zext i1 %tobool to i32
> +  %conv2 = sitofp i32 %conv to fp128
> +  %conv6 = sitofp i32 %conv to double
> +  %call3 = tail call i32 @g(fp128 %conv2)
> +  %call8 = tail call i32 @h(double %conv6)
> +  ret void
> +}
> +
> +declare i32 @f()
> +declare i32 @g(fp128)
> +declare i32 @h(double)
>
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