[PATCH][X86] SSE2 cvtsd2ss instruction expects two operands

[Quentin Colombet]

Hi Cameron,

I do not think this is quite right.

CVTSD2SS has three operands for the SSE variant.
Indeed, the converted operand is set to the low quadword (or doubleword) of the destination register ($dst), and the high quadword (doublewords) are left unchanged ($src1).

CVTSD2SS does what you want for the FP variant (one source one destination):

def CVTSD2SSrr  : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
                      "cvtsd2ss\t{$src, $dst|$dst, $src}",
                      [(set FR32:$dst, (fround FR64:$src))],
                      IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;


Am I missing something?

-Quentin

On Oct 15, 2013, at 12:28 PM, Cameron McInally <cameron.mcinally at nyu.edu> wrote:

> Hey guys,
> 
> Here is a small patch to fix the Int_CVTSD2SS patterns. This SSE2
> instruction expects two operands, not three.
> 
> Also, I do not have commit access.
> 
> Thanks,
> Cameron
> <Int_CVTSD2SS.patch>_______________________________________________
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